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Welcome to MOSIS

Wafer From prototype to production, MOSIS is a design engineer's single source for a wide variety of semiconductor processes offered by major foundries.

Costs are kept low by combining designs from many customers into multi-project wafer (MPW) runs. With prototype costs reduced, engineers can submit several variations of the same design to the same run, thus shortening time-to-market.

Final designs can then be submitted to MOSIS for low- medium volume production or dedicated Engineering wafer runs (COT).

Along with wafers and die, MOSIS provides a full range of packaging and bonding options for designs fabricated through our service.



MOSIS, CMP, and CMC Partner to Introduce a 3D-IC Process


Quick Links for...
  • New MOSIS Users
  • Experienced MOSIS Users
  • Purchasing Agents
  • Design and Test
  • Academic Institutions
  • Non U.S. Customers

  • Announcements and News
  • MOSIS 3-D Chip Alliance in June 2010 EE Times Article
  • Events - Job Openings
  • Other MOSIS Announcements

    Fabrication Processes
  • IBM - TSMC - ON Semi
  • austriamicrosystems - Peregrine



  • Fabrication Schedule

    JUL 19

     ON-SEMI C5F/C5N
     TSMC 0.18 µm
     TSMC 0.25 µm
     TSMC 40 nm
     TSMC 45 nm

    JUL 26

     AMS C18
     ON-SEMI C5F/C5N
     PEREGRINE GC
     TSMC 0.13 µm
     TSMC 65 nm

    AUG 02

     AMS H35B4D3
     IBM 7HV
     ON-SEMI I3T50
     TSMC 0.18 µm
     TSMC 0.25 µm
     TSMC 90 nm

    AUG 09

     IBM 10LPE
     IBM 8RF
     TSMC 0.18 µm
     TSMC 65 nm

    AUG 16

     AMS C35B4C3
     AMS C35B4O1
     IBM 7RF
     IBM 7RFSOI
     TSMC 0.18 µm
     TSMC 0.35 µm
     TSMC 40 nm
     TSMC 45 nm

    AUG 23

     TSMC 0.13 µm
     TSMC 65 nm

  • More...






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    4676 Admiralty Way, Marina del Rey, California 90292-6695 USA

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