|
|
TSMC Fabrication
Technology descriptions, MPW fabrication schedule, and vendor
document access procedures for the TSMC fabrication processes
available through MOSIS.
TSMC Fabrication Processes
The TSMC fabrication processes available through MOSIS include
0.35 µm CMOS, 0.25 µm CMOS, 0.18 µm
CMOS, and 0.13 µm CMOS.
TSMC Fabrication Schedule
MOSIS offers access to the TSMC multiproject wafer (MPW) runs. To be
considered ontime for an MPW run, layout and paperwork are due to
MOSIS by 1 PM PT (Pacific/California Time) on the date listed.
TSMC Design Kits
TSMC Design Kits are available upon approval for MOSIS customers.
How To Access TSMC Documents
General instructions for accessing TSMC design rules and cell
libraries through MOSIS.
|
Related Links
MOSIS Fabrication Processes
|
|
|
