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Taiwan Semiconductor (TSMC)
0.25 Micron
CL025/CR025 (CM025) Process
1. Process Description
This CMOS process has 5 metal layers and 1 poly layer. The process is
for 2.5 volt applications. A thick oxide layer can be used for 3.3
volt transistors. Designs for this process require Metal 5 in the pad
stack. Flip chip bumping is available from MOSIS. Please send e-mail
to support@mosis.com for more
information.
CL025 Process
Silicide block (RPO), thick gate oxide (3.3 V), ESD 3.3 V, and NT_N
options are available on multiproject runs.
This logic process uses non-epitaxial wafers. Epitaxial wafers are
available at an additional cost. Specify "epitaxial wafers" in the
"Options" section of the
Request for Custom Quote form
for pricing. To order epitaxial wafers, submit the Request for Custom
Quote and select the epitaxial fabrication option from either the
New Project,
Fabricate, or
Update form.
CR025 (CM025) Process
CR025 (CM025) (mixed-mode) offers the above layers of CL025 plus deep n-well,
ThickTopMetal (inductor), and MiM options. The Thick_Top_Metal option
must be explicitly specified with each design submission that requires
it. MiM (Cap_Top_Metal, also known as Metal 4 Prime, to Metal 4)
provides a capacitance of 1 fF/µm². This mixed signal/RF
process (CR025 (CM025) uses non-epitaxial wafers.
The CR025 (CM025) process offers three threshold voltages: nominal,
medium and Zero. Zero threshold voltage is also called depletion
threshold voltage. Nominal is the default. Medium and Zero are extra
cost options. For Medium you have a choice of N (VTM_N) or P (VTM_P)
or both. For Zero you have a choice of N (VTD_N) or P (VTD_P) or both
AND you must order Medium of the same type.
2. Design Rules
These processes support the following design rules
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Design Rules
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Lambda
(micro- meter)
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Feature Size
(micro- meter)
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Available
From
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SCN5M_SUBM
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0.15
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0.24
(after sizing)
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MOSIS in
HTML
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SCN5M_DEEP
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0.12
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0.24
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MOSIS in
HTML
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TSMC rules
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None
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0.24
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MOSIS (See Section 3)
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Note: Stacked contacts/vias are supported by this process.
Review the following
CMP and antenna guidelines which apply to both sets of design
rules.
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MOSIS Technology Codes
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See
Technology
Codes for TSMC 0.25 Micron Process.
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Important note about insulator layers
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On this process, TSMC requires that all features on the insulator
layers (CONTACT, VIA, VIA2, VIA3, VIA4) be of the single standard
size. There are no exceptions for pads, logos, or anything else. Large
openings are to be replaced by an array of standard sized openings.
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3.
TSMC Design Rules, Process Specifications, and SPICE
Parameters
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TSMC has sub-licensed MOSIS to distribute this information to approved
customers who have an account with MOSIS and submit the online
TSMC Access
Request form.
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4. Parametric Test Results and SPICE Model Parameters
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See
Test Results for TSMC_025SPPM runs.
5. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
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TSMC 0.25 Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time (weeks, approx.)
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Die Thickness
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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21 x 21 *
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55
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9 - 10
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~10 - 12 **
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~250 - 305 **
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30
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760
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* Smaller sizes are available.
** Contact support@mosis.com if
these thicknesses do not meet your requirements.
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Related Links
MOSIS-Supported TSMC Processes
TSMC Technology
Codes & Layer Maps
TSMC Document Access
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