The cell layout depicted is idealized. The actual layout we generate
varies from process to process, based on the foundry's own fill
rules. For those foundries that encourage, or at least allow, floating
layout in fill cells, we generate only the poly and metal layout; the
active, contact and via layers are not filled. For those foundries
that require that the fill cells be electrically grounded, we generate
the entire stack, so that the cell is electrically connected to the
substrate. We also extend the stack upward through as many metal
layers as required (all or all but the topmost). We also size various
of the layers to meet process rules and/or to alter the density
effect.
Currently, the only MOSIS foundry that requires grounded fill is
Agilent/ HP.
The "Antenna Rules" deal with process induced gate oxide damage caused
when exposed polysilicon and metal structures, connected to a thin
oxide transistor, collect charge from the processing environment
(e.g., reactive ion etch) and develop potentials sufficiently large to
cause Fowler Nordheim current to flow through the thin oxide. Given
the known process charge fluence, a figure of exposed conductor area
to transistor gate area ratio is determined which guarantees Time
Dependent Dielectric Breakdown (TDDB) reliability requirements for the
fabricator. Failure to consider antenna rules in a design may lead to
either reduced performance in transistors exposed to process induced
damage, or may lead to total failure if the antenna rules are
seriously violated.
The polysilicon rules require that the area of the polysilicon over
field oxide divided by the area of the transistor gate (thin oxide
area) must be less than Np (where Np is a limit that depends on the
process and on design targets). For example, a 200 µm long
by 1 µm wide polysilicon wire connected to two channel regions
of 2 µm X 0.6 µm and 1 µm X 0.6 µm
has an antenna ratio of 111. Usually the polysilicon rules are fairly
conservative, so the antenna ratio in this example may be in violation
of some fabricator's polysilicon antenna rule.
A similar calculation applies to metal wires connected to transistor
gates. In this case, you must first obey the Np:1 rule for any
polysilicon. Metal antenna rules can be a little more variable
depending upon how conservative a fabricator is in dealing with this
damage mechanism. The most conservative approach recognizes that
process induced damage is a cumulative effect. In this case, you
calculate the total area of the poly + metal1 + metal2 + metal3 +
... and divide by the area of the transistor channels connected to
this structure. This ratio must be less than Nm.
A less conservative metal antenna rule defines ratios for each metal
level (Nm1, Nm2, Nm3, etc.) and recognize that lower levels of metal
are protected by inter-level dielectric during the etch process for the
metal above. Other metal rules recognize that photoresist covers metal
lines during reactive ion etch, so the antenna rule only needs to
consider the area of the exposed metal edges. This results in rules
defined for area ratio calculations as follows: Ratio =
2[(L_metal+W_metal)*t_metal]/(W_channel*L_channel), where, W_metal,
L_metal, and t_metal are the width, length and thickness of the metal
line connected to a total channel area defined by W_channel by
L_channel.
If metal1 is connected to an active area junction and to a poly
structure connected to a transistor channel, then the Nm:1 rule is
relaxed. However, the poly Np:1 ratio rule still applies. The reason
for this exception is that charge induced current is safely shunted
through the junction to the substrate and, therefore, does not cause
gate oxide damage. The junction area ratio (A_total/A_junction) must
not be more than N_max:1. Note: A_total is the sum of poly and metal
area connected to a thin oxide region.
An additional absolute area rule is also imposed for additional safety
margin. The total area of exposed conductor that is electrically
connected to a gate channel area limited to A_max
µm². Other constraints may apply, but these constraints are
specific to a particular fabricator.
There are layout techniques to help deal with antenna ratio rules. For
example, if a design uses a large array of clocked devices connected
to a single clock source via a metal1 clock distribution structure then a
"cut and link" method can be used to moderate the antenna rule
effects. In this method, the metal1 distribution structure is divided
up into pieces of metal1 connected to gate structures such that the
antenna rule is obeyed. Short links from metal1 to metal2 then back
to metal1 connect the clock distribution structure in a way that it
prevents the total area of the clock distribution structure from being
connected to gate poly structures during metal1 etch. If the metal2
links are the minimum links necessary to make the connection, then the
current induced in the metal2 area is very small (Nm2 << metal2
rule).
Specific numbers for the antenna ratio rules are contained in design
rules for each fabricator. MOSIS customers can obtain this information
in the fabricator
rules.