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AMI Semiconductor Layer Map
ABN

This is the layer map for the AMI ABN 1.50 micron 2 metal, 2 poly layout rules (AMI_ABN), and only for those AMI vendor design rules. For designs that are laid out using other design rules (or technology codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below.

Layer GDS CIF Notes
N_WELL 1 A01
PBASE 2 A02 Optional
ACTIVE 3 A03
N_CHANNEL_FLD 4 A04 Derived from N_WELL when N_CHANNEL_FLD is completely absent from layout. See Note #1
POLY 9 A09
POLY2 10 A10 Optional
P_PLUS_SELECT 11 A11
N_PLUS_SELECT 12 A12
CONTACT 14 A14
METAL1 15 A15
VIA 16 A16
METAL2 17 A17
GLASS 18 A18
N_MINUS_IMPLANT 19 A19 Derived from N_PLUS_SELECT when N_MINUS_IMPLANT is completely absent from layout. See Note #1


Note #1: If this layer is present anywhere in the submitted design or anywhere in the design after instantiation, then MOSIS will not derive it. If this layer is not in the submitted design or anywhere in the design after instantiation, then MOSIS will derive that layer from the listed layers. MOSIS does not create a layer partially from a layer drawn by the customer and partially derived from other layers.


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