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MOSIS SCMOS Technology Codes and Layer Maps
SCN3M and SCN3M_SUBM
This is the layer map for the technology codes SCN3M and SCN3M_SUBM
using the MOSIS Scalable CMOS layout rules
(SCMOS), and only for SCN3M and SCN3M_SUBM. For designs that are
laid out using other design rules (or
technology codes),
use the standard layer mapping conventions of that design rule set.
For submissions in GDS format, the datatype is "0" (zero) unless
specified in the map below.
SCN3M_SUBM: Uses revised layout rules for better fit to sub-micron
processes (see
section 2.4)
Fabricated on
AMI 0.50 micron
process runs.
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