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MOSIS SCMOS Technology Codes and Layer Maps
SCN4ME and SCN4ME_SUBM
This is the layer map for the technology codes SCN4ME and SCN4ME_SUBM
using the MOSIS Scalable CMOS layout rules
(
SCMOS), and only for SCN4ME and SCN4ME_SUBM. For designs that are
laid out using other design rules
(or technology-codes),
use the standard layer mapping conventions of that design rule set.
For submissions in GDS format, the datatype is "0" (zero) unless
specified in the map below.
SCN4ME: Scalable CMOS N-well, 4 metal, 2 poly, polycide, no silicide
block, thick oxide option available.
SCN4ME_SUBM: Uses revised layout rules for better fit to sub-micron
processes (see MOSIS Scalable CMOS (SCMOS) Design Rules,
section
2.4).
Fabricated on
TSMC
and
AMIS 0.35 micron
process runs.
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