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MOSIS SCMOS Technology Codes and Layer Maps
SCN6M, SCN6M_SUBM, and SCN6M_DEEP
This is the layer map for the technology code SCN6M
using the MOSIS Scalable CMOS layout rules
(SCMOS),
and only for SCN6M. For designs that are laid out using other design
rules
(or technology-codes),
use the standard layer mapping conventions of that design rule set.
For submissions in GDS format, the datatype is "0" (zero) unless
specified in the map below.
SCN6M_SUBM: Scalable CMOS N-well, 6 metal, 1 poly, thick oxide option,
and supports silicide block. MiM (Cap_Top_Metal, also known as Metal
5
Prime, to Metal 5) capacitors are available. Uses revised layout
rules for better fit to sub-micron processes
(see
section 2.4)
SCN6M_DEEP: Uses revised layout rules for better fit to deep
sub-micron processes
(see
section
2.4)
Fabricated on
TSMC 0.18 micron
process runs.
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