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MOSIS SCMOS Technology Codes and Layer Maps SCNA and SCNE This is the layer map for the technology codes SCNA and SCNE using the MOSIS Scalable CMOS layout rules (SCMOS), and only for SCNA and SCNE. For designs that are laid out using other design rules (or technology-codes), use the standard layer mapping conventions of that design rule set. For submissions in GDS format, the datatype is "0" (zero) unless specified in the map below. SCNE: Two metal, two poly. Second polysilicon layer (poly2) can serve either as the upper electrode of poly capacitor or as a gate for transistors. SCNA: Same as SCNE, adds layers for vertical NPN transitor pbase. Layer GDS CIF CIF Synonym Rule Section Notes N_WELL 42 CWN   1   ACTIVE 43 CAA   2 PBASE 58 CBA   16 Optional, SCNA only POLY 46 CPG   3 N_PLUS_SELECT 45 CSN   4 P_PLUS_SELECT 44 CSP   4 POLY2 56 CP2 CEL 11, 12, 13 Optional CONTACT 25 CCC CCG 5, 6, 13   POLY_CONTACT 47 CCP   5 Can be replaced by CONTACT ACTIVE_CONTACT 48 CCA   6 Can be replaced by CONTACT POLY2_CONTACT 55 CCE   13 Can be replaced by CONTACT. METAL1 49 CM1 CMF 7 VIA 50 CV1 CVA 8 METAL2 51 CM2 CMS 9 GLASS 52 COG   10 PADS 26 XP   Non-fab layer used to highlight pads Comments -- CX     Comments Related Links Fabrication Schedule Customer Support MOSIS Products

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