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SCMOS Design Flow SCMOS Design Kits Projects submitted to MOSIS for fabrication can be designed using either layout design rules and layers specific to a process (vendor native rules) or (for some processes) vendor-independent, scalable rules (SCMOS rules). These rule sets cannot be mixed within a design. The table below contains links to design kits, technology files, cell libraries, IP, and other design support for a variety of CAD tools for various processes availble through MOSIS that use SCMOS rules. Foundry Comparable Process1 Technology Codes (Link to Layer Map) Lambda Design Kit Simulation DRC, LVS, Extraction Cell Libraries Pads TSMC 0.35 micron, 1P4M, Silicided, CL035 (TSMC35_SIL) SCN4M SCN4M_SUBM 0.25 0.20 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 NCSU CDK4 Tanner (SUBM)   CIF   GDS SCMOS_SUBM   CIF   GDS Magic NCSU CDK 0.35 micron, 2P4M, Polycided CM035 (TSMC35_P2) SCN4ME SCN4ME_SUBM 0.25 0.20 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 NCSU CDK4 Tanner (SUBM)   CIF   GDS Magic NCSU CDK 0.25 micron, 1P5M, CL025/CR025 (CM025) SCN5M_SUBM SCN5M_DEEP 0.15 0.10 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 NCSU CDK4 Tanner (DEEP)   CIF   GDS Virginia Tech (DEEP2) Oklahoma State (SUBM3) SCMOS_DEEP   CIF   GDS Magic 0.18 micron 1P6M CL018 CR018 (CM018) SCN6M_SUBM SCN6M_DEEP 0.10 0.09 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 NCSU CDK4 Oklahoma State (SUBM3) Virginia Tech (DEEP2)   ON Semi 0.50 micron, 1P3M, C5 SCN3M SCN3M_SUBM 0.35 0.30 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 Cadence, Diva NCSU CDK4 Tanner (SUBM)   CIF   GDS Oklahoma State (SUBM3) SCMOS_SUBM   CIF   GDS Magic NCSU CDK 0.50 micron, 2P3M, C5 SCN3ME SCN3ME_SUBM 0.35 0.30 NCSU Cadence Design Kit (CDK), Mentor ASIC Design Kit, Magic, Electric BSIM3v3 NCSU CDK4 Tanner (SUBM)   CIF   GDS Oklahoma State (SUBM3) SCN3ME_SUBM Magic NCSU CDK 1 MOSIS has not issued SCMOS design rules for some vendor-supported options. Most non-standard options (for example, medium threshold voltage) are available only for projects designed using the vendor set of layers and rules. 2 Virginia Tech offers a standard cell library for the TSMC 0.25 micron process technology based on MOSIS SCMOS_DEEP rules for use with Synopsys synthesis and Cadence place-and-route tools. 3 The Oklahoma State University standard cell library for the ON Semi 0.5, TSMC 0.25 and 0.18 micron process technologies is based on SCMOS_SUBM rules for use with Synopsys' synthesis tools and Cadence Design Systems' (CDS) Silicon Ensemble place-and-route tools. 4 The NCSU design kit contains LVS, HSpice. The Diva DRC deck contains all rules from the MOSIS SCMOS User's Manual 8.0 except for some DEEP rules and wide-metal rules. Related Links EDA Tools (Union College) Tale of an IC Design Engineer (SJSU) Design Resources and Cadence Tutorials (SJSU) Cadence Tutorial (Worcester Polytechnic Institute)

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