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IBM 10LPE/10RFE CMOS Process
65 Nanometer (65 nm)
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 65 nm CMOS 10LPE/10RFE technology
for prototype and low volume fabrication. This is the low-power,
rotated variant of the IBM 65 nm CMOS 10SF technology.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
Supply voltages are 1.2 V core and 2.5 V I/O. MOSIS offers this
CMOS process with two distinct metal stacks
A digital stack with 9 metal layers
M1, M2, M3, M4, M5, M6, BA, BB, and LB topmetal to DV (glass
cut). This is the IBM "9LB_6_02_00_00_LB" stack, with six thin metals
over low-K dielectric, two thick metals ("2x") over TEOS/FTEOS
dielectric, no 4x metal, LB topmetal, and QT/HT MiM
An analog stack with 8 metal layers
M1, M2, M3, M4, M5, BA, OA, and LD topmetal to DV (glass cut). This
is the IBM "8LD_5_01_00_01LD" stack, with five thin metals over low-K
dielectric, one thick metal ("2x") over TEOS/FTEOS dielectric, no "4x"
metals, one 12x metal, and LD topmetal.
10LPE/10RFE Supported Options
Please refer to the list of
10LPE/10RFE Supported
Options page for the options available by default on MOSIS MPW runs in this
technology.
Other configurations are available for dedicated runs, or on MPW runs
by prior arrangement. Please
contact MOSIS support for
additional details, e.g. costs.
Design Considerations
To insure that submitted data is on a 1 nm grid, please stream-out
at 1 DBU = 1 nm (Cadence 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM CMOS Design
Kits page are the only kits and files available.
MOSIS distributes "IBM" as opposed to "CP"
(Common
Platform) design kits.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
Layouts may be submitted to the 10LPE/10RFE process using either
technology code IBM_10LPE or IBM_10RFE. These are absolute synonymns to
MOSIS: "analog" and "digital" stacks may be submitted using either
technology code.
Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM CMOS
65 Nanometer
10LPE/10RFE Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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57
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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