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Options
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Masks
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Part Number
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Base Features for CMOS 10LPL (CMOS10LPe) Low Power
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N-well and p-well in substrate and an isolated p-well
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BF, N3
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ACLV gate orientation option
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Horizontal
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Oxide option Thin + thick oxide
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DG
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Regular-Vt + native-Vt + low-Vt +
high-Vt + regular DG I/O NFET
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NV, NR, DG, DE, JN
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Regular-Vt + low-Vt + high-Vt +
regular DG I/O PFET
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PV, PR, DG, DF
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Thin-oxide NCAP
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Thick-oxide NCAP
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DG
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Thin-oxide PCAP
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N3
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P+ polysilicon OP resistor
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OP
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N+ diffusion OP resistor
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OP
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N-well resistor
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Electrostatic discharge (ESD) devices
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OP
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Vertical natural capacitor (VNCAP)
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Precision p+ polysilicon RP resistor
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RP
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2
|
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Asymmetrical Drain FETs (ADFETs)
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KN, KP
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2
|
|
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Hyper-Abrupt (HA) Junction Varactor
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JD
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Vertical PNP bipolar transistor
|
OP
|
|
|
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Standard SRAM
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NR, PR
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|
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Electrically programmable eFUSE
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Passivation
|
LV (C4 only)
|
01L6953¹
|
|
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DV (Wirebond only)
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01L6995
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Digital Stack
|
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Options
|
Masks
|
Part Number
|
|
Inductor option
|
Native, thick wire inductor
|
|
|
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Two 2x copper levels in a TEOS/FTEOS dielectric with LB
|
WT, BA, WA, BB, VV, LB
|
2
|
|
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Eight Cu metal levels plus LB
|
|
|
|
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Nitride MiM capacitor
|
HT, QT
|
2
|
|
|
|
|
|
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Analog Stack2
|
|
Options
|
Masks
|
Part Number
|
|
One 2x copper level in TEOS/FTEOS with 12x thick copper and LD
|
WT, BA, JT, OA, VV, LD
|
2
|
|
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Eight Cu metal levels, including LD
|
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2
|
|
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BEOL inductor with JT, LD, OA
|
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2
|
|
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Nitride MiM capacitor
|
HT, QT
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2
|
|
|
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Metal Stacks 3
|
9-Metal Digital Metal Stack
9LB_6_02_00_00
|
|
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LB
|
|
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Bond metal
|
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VV
|
|
|
|
|
|
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BB
|
|
|
|
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WA
|
|
|
|
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2x thick metals in TEOS/FTEOS
|
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BA
|
|
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|
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WT
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M6
|
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V5
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M5
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V4
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M4
|
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V3
|
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M3
|
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1x thin metals
|
|
V2
|
|
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M2
|
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V1
|
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M1
|
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CA
|
|
|
|
|
|
|
8-Metal Analog Metal Stack
8LD_5_01_00_01
|
|
|
LD
|
|
|
Bond metal
|
|
VV
|
|
|
|
|
|
|
OA
|
|
|
12x metal
|
|
JT
|
|
|
|
|
|
|
BA
|
|
|
2x thick metal in TEOS/FTEOS
|
|
WT
|
|
|
|
|
|
|
M5
|
|
|
|
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V4
|
|
|
|
|
|
|
M4
|
|
|
|
|
V3
|
|
|
|
|
|
|
M3
|
|
|
1x thin metals
|
|
V2
|
|
|
|
|
|
|
M2
|
|
|
|
|
V1
|
|
|
|
|
|
|
M1
|
|
|
|
|
CA
|
|
|
|
|
|
|
1 Subject to availability at additional cost. Advance notice required by
contacting support@mosis.com.
2 This device can only be fabricated at one of IBM's foundries. All
other devices can be fabricated at any one of the
Common
Platform (CP) foundries. The CP is a collaboration between IBM
and several other foundries to provide advanced feature size
fabrication. Irrespective of which foundry is used, the designer can
be assured that their parts will behave as if they were fabricated at
IBM.
3Other configurations subject to availability with sufficient
notice to support@mosis.com.
|
