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IBM 10SF CMOS Process
65 Nanometer (65 nm)
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 65 nm CMOS 10SF technology
for prototype and low volume fabrication. C4 (IBM's flip chip
bumping) is available at an additional cost.
MOSIS offers this CMOS process as 8 metal layers (M1, M2, M3, M4, M5,
M6, BA, BB) plus LB (transfer) to DV (glass cut). This is the
IBM "9LB_6_02_00_00" stack, with six thin metals over low-K dielectric, two
thick metals ("2x") over TEOS/FTEOS dielectric, and no "4x" metals.
Supply voltages are 1.0 V core and 1.8, 2.5 V I/O.
10SF Supported Options
Please refer to the list of
10SF Supported Options
page for the options available by default on MOSIS MPW runs in this
technology.
Other configurations are available for dedicated runs, or on MPW runs
by prior arrangement. Please
contact
MOSIS support for additional details, e.g. costs.
Four Gate Oxide Thicknesses Available
Although there are four gate oxide thickness options, only three can
be present in any one design, and DG and TG are mutually exclusive.
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1.25 nm (thin)
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FETs
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LVT, RVT, HVT
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Vdd
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Max 1.0 V
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2.2 nm (intermediate)
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FETs
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EG (high-speed I/O FETs)
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Vdd
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1.2 V
1.5 V
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5.2 nm (thick)
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FETs
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DG (regular I/O FETs)
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Vdd
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1.8 V
2.5 V
3.3 V1
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6.8 nm
(also called thick)
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FETs
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TG (TG FETs)
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Vdd
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3.3 V1
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1
This device can only be fabricated at one of IBM's foundries. All
other devices can be fabricated at any one of the
Common
Platform (CP) foundries. The CP is a collaboration between IBM
and several other foundries to provide advanced feature size
fabrication. Irrespective of which foundry is used, the designer can
be assured that their parts will behave as if they were fabricated at
IBM.
Design Considerations
To insure that submitted data is on a 5 nm grid, please stream-out
at 1 DBU = 5 nm (Cadence 0.005, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM CMOS Design
Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 10SF process is IBM_10SF.
Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM CMOS
65 Nanometer
10SF Process
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Wafer Size
(milli- meters)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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300
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25 x 30
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60
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57
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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