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Options
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Masks
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Part Number
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Base Features for CMOS 10SF
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1
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N-well and p-well in substrate and an isolated p-well
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BF, N3
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1
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ACLV gate orientation option
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Horizontal
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1
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Oxide option
Thin + medium + thick oxide
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EG, DG
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1
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Low-Vt + zero-Vt + regular-Vt + high-Vt + regular I/O + high-speed I/O NFET
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DG, EG, XW, NV, NR, IN, JN, GN, DE
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1
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Low-Vt + regular-Vt + high-Vt + regular I/O + high-speed I/O PFET
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DG, EG, LW, PV, PR, IP, JP, GP, DF
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1
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Thin-oxide NCAP
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PV
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1
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Medium-oxide NCAP
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EG, IP
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1
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Thick-oxide NCAP
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DG, JP
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1
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Thin-oxide PCAP
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NV
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1
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P+ polysilicon OP resistor
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OP
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1
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N+ diffusion OP resistor
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OP
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1
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N-well resistor
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NW
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1
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Precision p+ polysilicon RP resistor
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RP
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1
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VNCAP (BEOL capacitor)
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M1/M6, BA, BB metal levels
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27R6144
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Vertical PNP bipolar transistor
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NV
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1
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TaN resistor
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K1
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1
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Deep trench (DZ) capacitor
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DZ
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1
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Inductor option
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Native, thick wire inductor
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1
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Standard SRAM
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1
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Electrically programmable eFUSE
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295233
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Two 2x TEOS wiring
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LB WT, BA, WA, BB, VV, LB
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42K4292
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8LM (9LB_6_02_00_00)
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M1, V1, M2, V2, M3, V3, M4, V4, M5, V5, M6, WT, BA, WA, BB
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45L8958
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DV
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(for Wirebond)
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01L6995
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LV
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(for C4 bumping)
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01L6953 2
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Aluminum wire bond
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[to LB]
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295232
|
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C4 plated (flip-chip)
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TM
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57P6150 2
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1 Part number available after T2 qualification. Features
marked limited have some restrictions on use. The base feature part
number represents standard processing for that technology. To ensure
the correct manufacturing of each part, a list of features must be
supplied to manufacturing. This table is intended to assist designers
in providing the necessary information to MOSIS. Feature availability
and limitations are shown here for reference only and might
change. Features must be evaluated based on current information as
part of the ordering process.
2 Contact
support@mosis.com for pricing
and further information.
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MOSIS Supported Metal Stack
9LB_6_02_00_00
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LB
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Bond metal
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VV
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BB
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WA
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2x thick metals
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BA
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WT
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M6
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V5
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M5
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V4
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M4
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V3
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1x thin metals
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M3
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V2
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M2
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V1
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M1
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CA
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