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IBM Semiconductor
0.50 Micron
5HP/5AM SiGe BiCMOS Process
Information vital to preparing and submitting a design for fabrication
in this process has been posted to the MOSIS
Secure Document Server.
All users must read the checking procedures and density
requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
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Process Family Description
MOSIS is offering access to the IBM 0.50 micron SiGe BiCMOS 5HP
technology for prototype and low volume fabrication.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
5HP Process
This SiGe BiCMOS process has 3 metal (M1+M2+LM) and 1 poly layers,
supports MiM (Q2 to M2). For more information, see the
IBM Blue Logic[tm] BiCMOS 5HP Process Description.
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5HP Supported Options
Please refer to the
List of
5HP Supported Options page for the options available on MOSIS MPW
runs in this technology. You may not submit a design containing any
options or metals stack which are not listed here without prior
arrangement with MOSIS.
While the process is capable of up to 5 metal layers, we offer
3. Other configurations are available for dedicated runs.
5AM Process
This SiGe BiCMOS process has 4 (M1+M2+MT+AM) metal and 1 poly layers,
supports MiM (Q2 to M2, nitride only).For more information, see the
IBM Blue Logic[tm] BiCMOS 5AM Process Description.
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5AM Supported Options
Please refer to the
List of
5AM Supported Options page for the options available on MOSIS MPW
runs in this technology. You may not submit a design containing any
options or metals stack which are not listed here without prior
arrangement with MOSIS. While the process is capable of up to 5 metal
layers, we offer 4 on multi-project wafer runs.
5HP and 5AM Design Considerations
To insure that submitted data is on a 25 nm grid, please stream-out at
1 DBU = 25 nm (Cadence 0.025, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
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IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM SiGe Design
Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 5HP process is IBM_5HP.
The technology code for the 5AM process is IBM_5AM.
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Parametric Test Results and SPICE Model Parameters
See
Test Results for IBM 0.50 micron runs.
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Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM SiGe BiCMOS
0.50 Micron
5HP/5AM Family Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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81 (5HP)
88 (5AM)
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
IBM Microelectronics
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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