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IBM Semiconductor
0.25 Micron
6HP/6DM SiGe BiCMOS Process
This process is available on
taxi and dedicated
runs (also known as COT or Customer Owned Tooling). It is not listed
on the MOSIS Multi-Project Wafer Run Schedule.
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs." IBM considers taxi
runs as MPW. Designs approved for fabrication on taxi runs may not
pass the more stringent design checks required for IBM production
runs.
Process Family Description
MOSIS is offering access to the IBM 0.25 micron SiGe BiCMOS 6HP/6DM
technology for prototype and low volume fabrication.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
6HP Process
This SiGe BiCMOS process has 6 metal (M1+M2+M3+M4+MT+AM) and 1 poly
layers, supports MiM capacitor (Q4/Q5, nitride only). The thick top
layer of metal can be used to make inductors.
6HP Supported Options
Please refer to the
List of 6HP Supported Options page for the options available on
MOSIS MPW runs in this technology. You may not submit a design
containing any options or metals stack which are not listed here
without prior arrangement with MOSIS. The stacked MiM option in this
process also allows for single MiMs to be fabricated: you do not need
to contact MOSIS about this. Other configurations are available for
dedicated runs.
6DM Process
This SiGe BiCMOS process has 7 metal (M1+M2+M3+M4+MT+E1+MA) layers and
supports MiM capacitor (Q4/Q5, nitride only). The two thick top
layers of metal can be used to make inductors.
6DM Supported Options
Please refer to the
List of 6DM Supported Options page for the options available on
MOSIS MPW runs in this technology. You may not submit a design
containing any options or metals stack which are not listed here
without prior arrangement with MOSIS. The stacked MiM option in this
process also allows for single MiMs to be fabricated: you do not need
to contact MOSIS about this. Other configurations are available for
dedicated runs.
6HP and 6DM Design Considerations
To insure that submitted data is on a 20 nm grid, please
stream-out at 1 DBU = 20 nm (Cadence 0.020, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM SiGe Design
Kits page are the only kits and files available.
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Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 6HP process is IBM_6HP.
The technology code for the 6DM process is IBM_6DM.
- Parametric Test Results and SPICE Model Parameters
See
Test Results for IBM 0.25 micron runs.
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Reticle/Wafer Size, Steps, Die and Wafer Thickness
IBM SiGe BiCMOS
0.25 Micron
6HP/6DM Process Family
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness *
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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10
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250
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10
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250
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30
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760
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* Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
IBM Microelectronics
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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