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IBM Semiconductor
0.25 Micron
6RF CMOS Process
6RF MPW Prices
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.25 micron mixed-mode CMOS 6RF
technology for prototype and low volume fabrication.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
A Cadence design kit (with Agilent ADS models) plus standard cell
libraries and IOs are
available.
This CMOS process has 5 metal layers (M1+M2+M3+MT+AM), supports
stacked MiM capacitor (Q3/Q4, nitride), thick top metal. For more
information, see the
IBM Blue Logic[tm] CMOS 6RF Process Description.
6RF Supported Options
Please refer to the
List of
6RF Supported Options page for the options available on MOSIS MPW
runs in this technology. You may not submit a design containing any
options or metals stack which are not listed here without prior
arrangement with MOSIS. The stacked MiM option in this process also
allows for single MiMs to be fabricated: you do not need to contact
MOSIS about this. While the process is capable of up to 6 metal
layers, we offer 5 on multi-project runs.
Design Considerations
To insure that submitted data is on a 10 nm grid, please stream-out at
1 DBU = 10 nm (Cadence 0.010, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted. RX density must pass
RECOMMENDED (20%) checking.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers
who have signed both the MOSIS customer agreement and the IBM Design
Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM CMOS Design
Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 6RF process is IBM_6RF.
Parametric Test Results and SPICE Model Parameters
See
Test Results for IBM
0.25 micron runs.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM CMOS
0.25 Micron
6RF Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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56
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
IBM Microelectronics
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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