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IBM SiGe & CMOS Processes

These IBM processes support ITAR regulated designs.

MOSIS has compiled the following chart comparing various features to help you better select which IBM process is most appropriate to your applicaiton.

IBM SiGe BiCMOS Processes

Feature Size Process Name CMOS   
Vdd [V]   
SiGe Ft [GHz] | BVceo(1) [V] Description
High   Performance   High   Breakdown  
0.13 µm 8HP 1.2, 2.5, 3.3   200 | 1.77     57 | 3.55     5th generation SiGe technology for advanced RADAR and mmWave applications.

8WL 1.2, 2.5, 3.3   103 | 2.4     54 | 4.7     Reduced performance, cost effective technology for wireless applications.

0.18 µm 7HP 1.8, 2.5, 3.3   120 | 2.0     20 | 4.75     4th generation SiGe technology best suited for wireless and high-speed switches.

7WL 1.8, 2.5, 3.3   60 | 3.3     29 | 6.0     Reduced performance, yet most cost effective SiGe technology offered.

0.25 µm 6HP/6DM 2.5, 3.3   47 | 3.3     27 | 5.7     3rd generation SiGe technology.

6WL 2.5, 3.3   60 | 3.2     29 | 6.0     A descendant of 7WL, it integrates 0.25 µm CMOS with the 7WL SiGe NPN.

0.35 µm 5HPE 3.3, 5.0   43 | 3.3     19 | 9.6     2nd generation SiGe technology with 0.35 µm CMOS and 0.5 µm SiGe NPN's.

5PAe 3.3, 5.0   35 | 5.5     25 | 7.5     Intended for power amplifier applications, this process features Through Wafer Vias.

0.50 µm 5HP 3.3   51 | 3.3     27 | 5.5     1st generation SiGe technology.

5AM 3.3   51 | 3.3     27 | 5.5     Similar to 5HP, but adds a thick top metal.

5DM 3.3   51 | 3.3     27 | 5.5     Similar to 5HP but adds two thick top metals for high-Q inductors.

5PA 3.3   51 | 3.3     24 | 7.0     Similar to 5AM, this process adds higher voltage NPN's for power amplifier applications.

A process comparison including Ft and Fmax can be found at the IBM BiCMOS Key Technology Specifications page.

(1) BVceo is not a voltage limit for biasing unless the NPN is operating under a forced Ib condition. Vce greater than BVceo is allowed for other bias configurations, lower base impedance leading to higher voltage limits.




IBM CMOS and IBM RF CMOS Processes

Feature Size Process Name Voltage (V)
Core   |   I/O
Description
45 nm 12SOI 1.0 | 0.9 This energy-saving SOI process is suitable for a broader range of consumer electronics, including digital TVs and high-end mobile applications.

65 nm 10SF 1.0 | 1.8, 2.5 Excellent for consumer electronics, wireless communications, and other applications requiring high performance or system-on-a-chip.

10LPe/RFe 1.2  |  2.5 Tailored for power-sensitive applications in wireless communications and consumer electronics.

90 nm 9SF 1.0  |  2.5 Ideal for leading-edge microprocessors, communications, and computer data processing applications.

9LP/RF 1.2  |  2.5 Use for low-cost, high performance wireless applications, as Bluetooth, WLAN, cellular handsets, mobile TV, WiMax, UWB and GPS.

130 nm 8RF-DM 1.2  |  2.5 Use for low-cost, high performance wireless applications as Bluetooth, WLAN, cellular handsets and GPS.

8RF-LM 1.2  |  2.5 Similar to 8RF-DM, but uses LM top metal.

180 nm 7SF 1.8  |  3.3 Use for high-performance graphics, communications, and data processing applications.

7RF 1.8  |  3.3 Ideally suited for RF and wireless applications, as Bluetooth, LANs, cellular phones and RF identification tags.

7HV 1.8/5/20/50 | Ideal solution for power management products, display drivers, printer and MEMS driver ICs.

7RF SOI 1.8  |  3.3 Optimized for RF switch applications, integrate multiple analog functions into single-chip solutions for mobile devices.

250 nm 6RF 2.5  |  3.3 This RF CMOS process is adapted for high frequency applications with a variety of passives (as high Q inductors, MIM and MOS capacitors, and MOS varactors) for mixed-signal and RF applications.




Design Interfaces
You can request the IBM design kit (design rules, models, and Cadence and Agilent ADS design kits) by following the instructions on the MOSIS web site at IBM Design Rules, Process Specifications, and SPICE Parameters page.

ADS support for IBM is RFDE/Dynamic-Link, and can only be used together with the IBM Cadence design environment.

Design interface (design kit, services) are available for these processes.


IBM Microelectronics Foundry IBM Business Partners




Related Links
  • IBM Design Kits For CMOS Processes
  • IBM Design Kits For SiGe Processes
  • IBM Technology Technology Codes & Layer Maps
  • IBM Document Access
  • ITAR Instructions
  • Checking and Error Disposition
  • IBM Taxi Runs





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