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ON Semiconductor
(formerly AMIS)
0.50 Micron
C5 Process


Process Family Description
This non-silicided CMOS process has 3 metal layers and 2 poly layers, and a high resistance layer. Stacked contacts are supported. The process is for 5 volt applications. MOSIS orders epi wafers for this process. For further information, see the AMIS Mixed Signal Foundry Services web page.

C5N Process
PiP (poly2 over poly) capacitors (950 aF/µm²) and the HRP (High Resistance) option are available on multiproject runs.

C5F Process
The C5F process offers the above layers of C5N plus Thick_Gate, N_Minus_Implant (Npblk), and P_Minus_Implant (Ppblk).

Design Rules
This process supports the following design rules.

Design Rules Lambda1 Feature Size1 Availablility
ON Semi C5F/N Rules n/a 0.60 MOSIS, ON Semiconductor

SCMOS_SUBM 0.30 0.60 MOSIS in HTML

SCMOS 0.35 0.60
(after sizing)
MOSIS in HTML

1Values in micrometers (µm)

Review the CMP and antenna guidelines which apply to both sets of design rules.


MOSIS Technology Codes
See Technology Codes for ON Semiconductor C5F/N Process.

Important note about pads
The bonding pads on designs submitted to these runs should have metal2 (and via2) under the metal3. If these guidelines are not followed, metal lifting problems can occur.

ON Semiconductor Design Rules, Process Specifications, and SPICE Parameters
ON Semiconductor has sub-licensed MOSIS to distribute this information to customers who do not have a MyAMIS or MyON account. To obtain any of these items you must have an account with MOSIS, submit the on-line ON Semiconductor Access Request, then sign both the Confidentiality Agreement (CDA) and Design Kit License Agreement (DKLA).

Parametric Test Results and SPICE Model Parameters
See Test Results for ON Semiconductor C5F/N runs.


Reticle/Wafer Size, Steps, Turnaround Time, Wafer and Die Thickness

ON Semiconductor C5 Process
Wafer Size
(inches)
Reticle Size (mili- meters, approx.) Reticle Copies Stepped on Wafer (approx.) Turn- around Time (weeks, approx.) Die Thickness
(+/- .5 mil)
Wafer Thickness
Mils Micro- meters Mils Micro- meters
8 21 x 21 55 10 - 12 10 250 30 760



Related Links
  • MOSIS-Supported ON Semiconductor Processes
  • ON Semiconductor Technology Codes & Layer Maps
  • ON Semiconductor Document Access





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