ARM (was Artisan) Library

INTRODUCTION AND EXPLANATION

These instructions are for university account holders only.
If your organization is not affiliated with a university, please see the ARM section on the MOSIS Digital Design Flow page.

ARM makes standard cells, I/O libraries, and memory generators for selected processes available through MOSIS to universities for use in designs fabricated through MOSIS.

These libraries are front-end kits only. They do not contain layout information, SPICE, or netlists.

If you have not yet gained access to these libraries, please see ARM Library Access for Universities.

Your place-and-route environment can, for example, provide a good estimate of circuit timing using the front-end kit's abstractions. They are not intended for SPICE-level design.

Using these front-end-only kits can create some limitations to the design process. It is not possible to do full DRC, full extraction/LVS, or full antenna checking. The entire process depends on your place and route environment working in "correct by construction" mode.

SUBMISSION

Submit your design at least one week prior to the run closing deadline. In the SPECIAL HANDLING parameter, request "Instantiation of ARM IP." Explicitly list the names and versions of the library or libraries from which you want MOSIS to instantiate.

MOSIS will check whether you are using the most recent release of that library, and if not, the design will be rejected.

Your GDS file may contain either calls to those cells without a corresponding cell in the file, or a call to a dummy cell. If you use a dummy cell, the dummy cell must contain no hierarchy in itself. We replace those calls to point to real layout.

Be careful: this process is case-sensitive. Do not upshift/downshift your cellnames during tapeout.

SUBMISSION EXAMPLE

In this example, the IBM_7RF design requires standard cells, ML-topmetal I/O (pads), and three memories: one ROM, and two single-port SRAM modules.

The design team submits their design minus the ARM cell libary at least one week prior to the run closing deadline, and receives the following message from the MOSIS front-end computers:

Your project has failed the MOSIS Manufacturability Review and will NOT be fabricated until the Project Errors noted below are resolved.

Project Errors:
structure not found in primary file: EDFFTRX1
structure not found in primary file: NAND3BX1

Project Status:
Design 70001 status: FAILED

This error message is normal when sending an incomplete layout to MOSIS. Do not re-submit your layout at this point.

The designer included the following information in the Special Handling parameter of the Fabrication Request sent along with the layout:

SPECIAL-HANDLING:

Instantiation of ARM IP requested.

Libraries and generators required:
1. ibm-cmrf7sf-rvt_io-gp-18-33-50-il-v10_2005q2v1
(pads: please use GDS for "arti_ibm18io_6lm_ml_i")
2. ibm-cmrf7sf-1.8v_sc-x_2005q3v1 (std cells)
3. ibm-cmrf7sf-1.8v_rom-via-hd-v10_2005q2v2 (ROM)
4. ibm-cmrf7sf-1.8v_sram-sp-v10_2005q2v1 (1-port SRAM)

Memory cell .spec files:
rom1kw.spec use with: ibm-cmrf7sf-1.8v_rom-via-hd-v10_2005q2v2
sram8kb.spec use with: ibm-cmrf7sf-1.8v_sram-sp-v10_2005q2v1
sram8kw.spec use with: ibm-cmrf7sf-1.8v_sram-sp-v10_2005q2v1

Please contact me to obtain the three .spec files. The following are not examples of clear ARM designations:

"the ARM std cells for 8RF"
"see tpz873nez_5lm.lef Date: Thu Sep 5 10:21:34 2002"

MOSIS will check whether you are using the most recent release of that library, and if not, the design will be rejected.

If you are using the most recent release(s), MOSIS contacts the design team within a few days with instructions on how to send the three .spec files, instantiates into the incomplete submitted GDS, substitutes the layout, and informs them of any issues.

The procedure is manual and labor intensive. Be certain you are submitting final layout before requesting instantiation. Do not send any Update Requests after the file has been instantiated, as this will undo the instantiation.

INSTANTIATION

MOSIS will instantiate full layouts for you when you are ready to fabricate your chip. We assume you will create a GDS file such as that produced by Silicon Ensemble which contains unresolved calls to ARM cells and pads.

This process has proved to be reliable. We instantiate about 15 to 20 designs a year, and we've never experienced a failure.

SPECIAL NOTE ON MEMORY OR REGFILE GENERATORS

If you are using memory or regfile generators, MOSIS will also need

the exact name and version of the generator,
the .vclef file which you used during place-and-route, and
the memory's .spec file.

We will feed your .spec file to our back-end copy of the same generator to produce the memory layouts. The .vclef file which we generate must match the .vclef file which you have sent to us. You must provide an entry in SPECIAL HANDLING for each distinct memory which MOSIS will be required to build for you, as shown in the example above.

If you don't supply both the .spec and .vclef files, we won't be able to instantiate the memory. Send these files in an e-mail message to support@mosis.com with a subject line of: "Instantiation files for design xxxx," where "xxxx" is your design number. Do not send either the .spec or .vclef file in SPECIAL HANDLING.

WARNING: If you forget to write out a .spec file at the same time you generate your synthesis views, you must then come in afterwards and try to reproduce that setup. If you do that, you must then use the .spec file you create to re-generate a "check" set of synthesis views (the documentation with the generator teaches how to do this) and then compare ("grep") the check set against the original set that you used for synthesis and place&route. All of those views (".lef" files, footprint etc.) must match.

ADDITIONAL RESTRICTIONS

You are not permitted to see the resulting complete GDS. MOSIS will not provide you with the GDS for your instantiated layout.

MOSIS cannot make any meaningful DRC results available, as the DRC polygons reveal details of the ARM cell layouts.

MOSIS never runs LVS on customer projects. LVS is a design issue: you have a schematic, and you have a layout. MOSIS never handles any schematics.

You cannot obtain cell layouts from MOSIS, nor will MOSIS refer you to ARM to obtain them.