Cadence® Design Flows with MOSIS
A variety of design flows (digital, analog, mixed-signal) can be used with Cadence tools to create designs for processes accessed by MOSIS.
Technology files and design kits for a variety of Cadence tools are available via the MOSIS document server.Synthesis to place and route design flows are available for selected processes using standard cell libraries and memory generators, e.g., the ARM/Artisan libraries.
MOSIS supports designs in vendor rules as well as SCMOS layout rules. Some members of the Cadence University Software Program have created design kits, technology files, etc., for various MOSIS processes using SCMOS rules.
One key example is the NCSU Cadence Design Kit (CDK), which focuses on supporting full-custom CMOS IC design.
Virginia Tech offers a standard cell library for the TSMC 0.25 and 0.18 process technologies based on MOSIS SCMOS_DEEP rules for use with Synopsys synthesis and Cadence place and route tools.
David Parent of San Jose State University offers a tutorial for using CDS tools (PDF), and a CDS tools FAQ (HTML). The tutorial is based on the NCSU design kit, and follows the design flow used by Worcester Polytechnic Institute (WPI).
An online Cadence Design Tools Tutorial is available from WPI.
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Page update effective September 1, 2011.