Digital Design Flow
Synthesis to place and route (with verification) design flows are available as listed below.
Aragio
Aragio offers I/Os (pads), and memory generators to commercial firms for the IBM 65nm (10SF, 10LPe) processes. Universities can access the complete front-end views I/O cells (behavioral, synthesis, simulation, place, and route) for the IBM 10LPe process. GDS layouts are not distributed to university users, instead these are instantiated by MOSIS prior to fabrication. See Aragio Library Access for Universities for additional information.
ARM (was Artisan)
ARM (was Artisan) offers free digital standard cell libraries, I/Os (pads), and memory generators to commercial firms for the IBM (9LP/RF), and 0.13 micron (8RF-DM, 8RF-LM) processes; the TSMC 65 nm, 90 nm, 0.13 micron (CL013G and CR013G/CM013G), 0.18 micron (CL018 and CR018/CM018), and 0.25 micron (CL025 and CR025/CM025) processes.
For more information from ARM, see their Physical IP Product page.
Universities can access the complete front-end views of core, I/O cells, and memory generators (behavioral, synthesis, simulation, place, and route) for the above processes. GDS layouts are not distributed to university users, instead these are instantiated by MOSIS prior to fabrication. See ARM Library Access for Universities for additional information.
Cadence
Process design kits (PDKs), et al., are available via the MOSIS secure document server.
Mentor
Technology files for a variety of tools are available via the MOSIS secure document server.
Synopsys
Technology files for a variety of tools are available via the MOSIS secure document server.
Virage
Standard cells and memories for the IBM 10LPe/RFe process are available from Virage Logic for MOSIS commercial and academic customers.