SCMOS Design Kits
SCMOS Design Flow
Projects submitted to MOSIS for fabrication can be designed using either layout design rules and layers specific to a process (vendor native rules) or (for some processes) vendor-independent, scalable rules (SCMOS rules). These rule sets cannot be mixed within a design.
The table below contains links to design kits, technology files, cell libraries, IP, and other design support for a variety of CAD tools for various processes available through MOSIS that use SCMOS rules.
1 MOSIS has not issued SCMOS design rules for some
vendor-supported options. Most non-standard options (for example,
medium threshold voltage) are available only for projects designed
using the vendor set of layers and rules.
2 Virginia Tech offers a standard cell library for the TSMC 0.25 micron process technology based on MOSIS SCMOS_DEEP rules for use with Synopsys synthesis and Cadence place-and-route tools.
3 The Oklahoma State University standard cell library for the ON Semi 0.5, TSMC 0.25 and 0.18 micron process technologies is based on SCMOS_SUBM rules for use with Synopsys' synthesis tools and Cadence Design Systems' (CDS) Silicon Ensemble place-and-route tools.
4 The NCSU design kit contains LVS, HSpice. The Diva DRC deck contains all rules from the MOSIS SCMOS User's Manual 8.0 except for some DEEP rules and wide-metal rules.
EDA Tools (Union College)
Cadence Tutorial (Worcester Polytechnic Institute)