Design Tools

SCMOS Design Flow

A variety of CAD tools are available to to create designs for processes that support SCMOS rules.

Cadence

Some members of the Cadence University Software Program have created design kits, technology files, etc., for various processes accessed by MOSIS using SCMOS rules. One key example is the NCSU Cadence Design Kit (CDK), which focuses on supporting full-custom CMOS IC design.

Virginia Tech offers a standard cell library for the TSMC 0.25 and 0.18 process technologies based on MOSIS SCMOS_DEEP rules for use with Synopsys synthesis and Cadence place-and-route tools.

Tanner

Tanner generated standard cells and pads for SCN3M_SUBM and SCM3ME_SUBM (ON Semi 0.5), SCN4M_SUBM (TSMC 0.35), and SCN5M_DEEP (TSMC 0.25) technologies. Pads are not available.

Mentor Graphics

Mentor Graphics supports Technology Design Kits for Mentor's Analog/Mixed-Signal IC Flow, including kits for several processes accessed by MOSIS. For more information, please refer to

Mentor Nanometer IC Design Environment

Mentor Technology Design Kit

Higher Education Program for the ASIC Design Kit