Design
A variety of design flows (digital, analog, mixed-signal) can be used with a number of different CAD tools, technology files, design kits, libraries and IP to create designs for processes accessed by MOSIS.
Design Kits
Design kits (PDKs), technology files, etc. (see design kit summary) that support a variety of CAD tools, e.g. Cadence, Mentor, Synopsys and Tanner. Except where noted, these are distributed free of charge and are made available (other than austriamicrosystems) through our document server after signature of the MOSIS customer agreement and the vendor required agreements.
Design Rules
Vendor design rules, SPICE models, etc. are available for each process. MOSIS provides electrical test data and SPICE parameters from MOSIS measurements on most MPW (multiproject wafer) runs. Projects submitted to MOSIS for fabrication can be designed using either the vendor's native design rules (specific to a process) or (for some processes) the SCMOS vendor-independent, scalable rules. These rule sets cannot be mixed within a design. SCMOS kits, cells and technology files are available.
Standard Cells, IP
Standard cell libraries enabling synthesis to place and route design flows are available for selected processes.
Standard cell libraries, I/Os (pads), and memory generators for various processes are available from ARM; university support for these libraries is available through MOSIS.
MOSIS commercial customers can contact Aragio directly. Universities can access Aragio front-end view I/O cells for the IBM 10LPe process through MOSIS.
Standard cells and memories for the IBM 10LPe/RFe process are available from Virage Logic for MOSIS commercial and academic customers.
ChipEstimate.com is a resource for chip size estimation and available IP.
Additional IP is available through MOSIS