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AMI Semiconductor Layer Map
C3O
This is the layer map for the AMIS C3O 0.35 micron 4 metal, 2 poly
(non-silicided) layout rules (AMI_C3O), and only for those AMI vendor
design rules. For designs that are laid out using other design rules
(or
technology-codes), use the standard layer mapping conventions of
that design rule set. For submissions in GDS format, the datatype is
"0" (zero) unless specified in the map below.
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Layer
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GDS
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CIF
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Notes
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ACTIVE
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1
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A01
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N_WELL
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2
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A02
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N_CHANNEL_FLD
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3
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A03
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Derived from N_WELL when N_CHANNEL_FLD is completely absent from
layout. See Note #1
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POLY
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4
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A04
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N_PLUS_BLOCK
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5
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A05
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Derived from P_PLUS_SELECT when N_PLUS_BLOCK is completely absent from
layout. See Note #1
AMI calls this layer N_PLUS_SELECT and further requires that it be a
copy of P_PLUS_SELECT. It is functionally an N_PLUS_BLOCK layer; the
drawn regions will not receive the n+ implant.
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P_PLUS_SELECT
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6
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A06
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CONTACT
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8
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A08
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METAL1
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9
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A09
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VIA1
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10
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A10
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METAL2
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11
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A11
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VIA2
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12
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A12
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METAL3
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13
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A13
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VIA3
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15
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A15
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METAL4
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16
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A16
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CAP_POLY (POLY2)
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26
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A26
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Optional
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HRP (HIGH RESISTANCE)
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27
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A27
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GLASS
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14
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A14
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Note #1:
If this layer is present anywhere in the submitted design or anywhere
in the design after instantiation, then MOSIS will not derive it. If
this layer is not in the submitted design or anywhere in the design
after instantiation, then MOSIS will derive that layer from the listed
layers. MOSIS does not create a layer partially from a layer drawn by
the customer and partially derived from other layers.
Related Links
Fabrication Schedule
Customer Support
MOSIS Products
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