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IBM 8RF-LM CMOS Process
0.13 Micron
Information vital to preparing and submitting a design for fabrication
in this process has been posted to the MOSIS
Secure Document Server.
All users must read the checking procedures and density
requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read
the IBM policy described in
"Checking and
Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.13 micron CMOS 8RF-LM technology
for prototype and low volume fabrication.
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required: contact
support@mosis.com.
This CMOS process offers up to 8 metal layers. MOSIS is supporting 8
metal layers, 2-thick (M1, M2, M3, M4, M5, M6, MQ, LM) plus TD
(transfer) to DV (glass cut). Supply voltages are 1.2 V core and 2.5
V I/O.
8RF-LM Supported Options
Please refer to the
List
of 8RF-LM Supported Options
page for the options available on MOSIS MPW runs in this technology.
You may not submit a design containing any options or metals stack
which are not listed here without prior arrangement with MOSIS. Other
configurations are available for dedicated runs, including 8SFG.
Design Considerations
To insure that submitted data is on a 10 nm grid, please stream-out at
1 DBU = 10 nm (Cadence 0.010, not 0.001).
8SFG Artisan libraries using High-Vt devices are not compatible with
8RF-LM.
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and
Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers
who have signed both the MOSIS customer agreement and the IBM Design
Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell
libraries, and files listed on the
IBM CMOS Design
Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 8RF-LM process is IBM_8RF.
Parametric Test Results and SPICE Model Parameters
See
Test Results for IBM 0.13 micron runs.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
IBM CMOS
0.13 Micron
8RF-LM Process
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Wafer Size
(inches)
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Reticle Size (milli- meters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time*
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Die Thickness
(+/- .5 mil)
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Bumped Die Thickness **
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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18 x 20
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60
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73
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10
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250
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10
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250
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30
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760
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* Calendar days from release to manufacturing. Does not include
dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe
your requirements in the SPECIAL-HANDLING parameter of your New
Project, Fabrication, or Update Request.
IBM Microelectronics
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Related Links
MOSIS-Supported IBM Processes
IBM Technology
Codes & Layer Maps
IBM Document Access
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