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Taiwan Semiconductor (TSMC)
0.18 Micron
CL018/CR018 (CM018) Process
1. Process Description
This CMOS process has 6 metal layers and 1 poly layer. The process is
for 1.8 volt applications. A thick oxide layer can be used for 3.3
volt transistors. Designs for this process require Metal 6 in the pad
stack. Flip chip bumping is available from MOSIS. Please send e-mail
to support@mosis.com for more
information.
CL018 Process
Silicide block, thick gate oxide (3.3 V), and NT_N options are
available on multiproject runs.
This logic process uses non-epitaxial wafers. Epitaxial wafers are
available at an additional cost. Specify "epitaxial wafers" in the
"Options" section of the
Request for Custom Quote form
for pricing. To order epitaxial wafers, submit the Request for Custom
Quote and select the epitaxial fabrication option from either the
New Project,
Fabricate, or
Update form.
CR018 (CM018) Process
CR018 (CM018) (mixed-mode) offers the above layers of CL018, plus deep n_well,
ThickTopMetal (inductor), high-resistance poly, and MiM. The
Thick_Top_Metal option must be explicitly specified with each design
submission that requires it. MiM (Cap_Top_Metal, also known as Metal
5 Prime, to Metal 5) provides a capacitance of 1 fF/µm².
This mixed signal/RF process uses non-epitaxial wafers.
The CR018 (CM018) process offers two threshold voltages: nominal and
medium. Nominal is the default. Medium is an extra cost option. You
have a choice of N (VTM_N) or P (VTM_P) or both.
2. Design Rules
These processes support the following design rules
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Design Rules
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Lambda
(micrometer)
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Feature Size
(micrometer)
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Available From
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SCN6M_SUBM
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0.10
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0.18
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MOSIS in
HTML
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SCN6M_DEEP
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0.09
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0.18
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MOSIS in
HTML
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TSMC rules
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None
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0.18
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MOSIS (See Section 3)
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Note: Stacked contacts/vias are supported by this process.
Review the following
CMP and antenna guidelines which apply to both sets of design
rules.
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MOSIS Technology Codes
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See
Technology
Codes for TSMC 0.18 Micron Process.
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3.
TSMC Design Rules, Process Specifications, and SPICE
Parameters
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TSMC has sub-licensed MOSIS to distribute this information to approved
customers who have an account with MOSIS and submit the online
TSMC Access
Request form.
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4. Parametric Test Results and SPICE Model Parameters
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See
Test Results for TSMC_018 runs.
5. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
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TSMC 0.18 Process
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Wafer Size
(inches)
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Reticle Size (millimeters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time (weeks, approx.)
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Die Thickness
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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21 x 21 *
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55
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10 - 11
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10
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250
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30
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760
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* Smaller sizes are available.
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Related Links
MOSIS-Supported TSMC Processes
TSMC Technology
Codes & Layer Maps
TSMC Document Access
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