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Taiwan Semiconductor (TSMC)
0.13 Micron
CL013LP Process
1. CL013LP Process (Logic) Description
This process is the TSMC 0.13 1P8M FSG 1.5/2.5 V low power
process.
This process has 1 poly layer, 8 metals. The process is for 1.5 volt
applications. A thick oxide layer can be used for 2.5 volt
transistors.
This process uses non-epitaxial wafers. Epitaxial wafers are
available at an additional cost. Specify "epitaxial wafers" in the
"Options" section of the
Request for Custom Quote form
for pricing. To order epitaxial wafers, submit the Request for Custom
Quote and select the epitaxial fabrication option from either the
New Project,
Fabricate, or
Update form.
2.
TSMC Design Rules, Process Specifications, and SPICE
Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved
customers who have an account with MOSIS and submit the online
TSMC Access
Request form.
Review the following
CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
Only the TSMC design rules will be supported for this technology.
MOSIS Technology Codes
See
Technology
Codes for TSMC CL013LP Process.
3. Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
4. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
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TSMC CL013LP Process
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Wafer Size
(inches)
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Reticle Size (millimeters, approx.)
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Reticle Copies Stepped on Wafer (approx.)
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Turn- around Time (weeks, approx.)
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Die Thickness
(+/- .5 mil)
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Wafer Thickness
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Mils
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Micro- meters
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Mils
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Micro- meters
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8
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21 x 21 *
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55
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13 - 14
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~10 - 12 **
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~250 - 305 **
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30
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760
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* Smaller sizes are available.
** Contact support@mosis.com if
these thicknesses do not meet your requirements.
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Related Links
MOSIS-Supported TSMC Processes
TSMC Technology
Codes & Layer Maps
TSMC Document Access
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