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Taiwan Semiconductor (TSMC) 0.13 Micron CL013LV Process 1. CL013LV Process (Logic) Description This process is the TSMC 0.13 1P8M FSG 1.0/2.5 V low voltage process. This process has 1 poly layer, 8 metals. The process is for 1.0 volt applications. A thick oxide layer can be used for 2.5 volt transistors. 2. TSMC Design Rules, Process Specifications, and SPICE Parameters TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request form. Review the following CMP and antenna guidelines which apply to this process. Design rules supported by this technology Only the TSMC design rules will be supported for this technology. MOSIS Technology Codes See Technology Codes for TSMC CL013LV Process. 3. Parametric Test Results and SPICE Model Parameters Contact support@mosis.com. 4. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness TSMC CL013LV Process Wafer Size (inches) Reticle Size (millimeters, approx.) Reticle Copies Stepped on Wafer (approx.) Turn- around Time (weeks, approx.) Die Thickness (+/- .5 mil) Wafer Thickness Mils Micro- meters Mils Micro- meters 8 21 x 21 * 55 13 - 14 ~10 - 12 ** ~250 - 305 ** 30 760   * Smaller sizes are available. ** Contact support@mosis.com if these thicknesses do not meet your requirements. Related Links MOSIS-Supported TSMC Processes TSMC Technology Codes & Layer Maps TSMC Document Access

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