|
|
Taiwan Semiconductor (TSMC)
0.18 Micron
CL018LV Process
1. CL018LV Process (Logic) Description
This process is the TSMC 0.18 1P6M 1.5/3.3 V low voltage
process.
This process has 1 poly layer, 6 metals, and is for 1.5 volt
applications. A thick oxide layer can be used for 3.3 volt
transistors.
2.
TSMC Design Rules, Process Specifications, and SPICE
Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved
customers who have an account with MOSIS and submit the online
TSMC Access
Request form.
Review the following
CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
Only the TSMC design rules will be supported for this technology.
MOSIS Technology Codes
See
Technology
Codes for TSMC CL018LV Process.
3. Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
4. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
|
TSMC CL018LV Process
|
Wafer Size
(inches)
|
Reticle Size (millimeters, approx.) (1)
|
Reticle Copies Stepped on Wafer (approx.)
|
Turn- around Time (weeks, approx.) (2)
|
Die Thickness (3)
(+/- .5 mil)
|
Wafer Thickness (3)
|
|
Mils
|
Micro- meters
|
Mils
|
Micro- meters
|
|
8
|
21 x 21
|
55
|
6 - 7
|
~10 - 12
|
~250 - 305
|
30
|
760
|
(1) Smaller sizes are available.
(2) Packaging not included in
turnaround time.
(3) Contact
support@mosis.com if these
thicknesses do not meet your requirements.
|
Related Links
MOSIS-Supported TSMC Processes
TSMC Technology
Codes & Layer Maps
TSMC Document Access
|
|
|
