Report generated: 27-Jun-2002 ORGANIZATION DESCRIPTION ---------------------------------------- --------------------------------------------------- Alfred University misc analog parts Assiut University This project is student project and has been approved by MOSIS Educational Program (MEP).The account name : Assiut University ACCOUNT name : 3180-MEP-INS/ASSIUTU-EE Boise State University francis's chip Boise State University kegan's chip Boise State University curtis' chip Boise State University a chip Boise State University a chip Boise State University Jose's chip Boise State University tim's chip Boise State University scott's chip Boise State University r-2r chip Boise State University schottky diodes Boise State University Schottky diode test structurs for EE515 Boise State University CMOS filter Boise State University test structures Boise State University analog test structures Boise State University Bill's chip with test structures Boise State University chip1 from Spring 2002 EE410 Boise State University chip2 from Spring 2002 EE410 Boise State University chip3 from Spring 2002 EE410 Boise State University chip4 from Spring 2002 EE410 Boise State University chip5 from Spring 2002 EE410 Boise State University chip6 from Spring 2002 EE410 Boise State University chip7 from Spring 2002 EE410 Brigham Young University cameron_wilde's ECE 451/445 class project Brigham Young University ben_stevenson's ECE 451 class project Brigham Young University bryant_smith's ECE 451 class project Brigham Young University don_bigler's ECE 451 class project Brigham Young University jacob_evans's ECE 451 class project Brigham Young University kevin_harper's ECE 451 class project Brigham Young University mary_sanders's ECE 451 class project Brigham Young University travis_williams's ECE 451 class project Brigham Young University rick_demille's ECE 451 class project Brigham Young University james_davis's ECE 451 class project Brigham Young University nathan_reynolds's ECE 451 class project Brigham Young University brian and emy lefevre's project Brigham Young University ben_johnson's ECE 451 class project Brigham Young University benjamin_wright's ECE 451 class project Brigham Young University brandon_langford's ECE 451 class project Brigham Young University jeff_bowden's ECE 451 class project Brigham Young University dan_carver's ECE 451 class project Brigham Young University justin_fitzpatrick's ECE 451 class project Brigham Young University joshua_parker's ECE 451 class project Brigham Young University randon_richards's ECE 451 class project Brown University This chip contains control and sequence logic for a system that will provide amplification/multiplexing of neural signals in a low power array sensor. The control is implemented in dynamic logic and this first step is to be sure that power Brown University and speed can be met while preparing for a later more integrated system. California State University Northridge digital game circuits California State University Northridge more games California State University Northridge signal gen. California State University Sacramento Four independent voltage-to-frequency converters Cinvestav The project contains a design of a switched-current sigma-delta modulator and some test structures Cinvestav The project contains a design of a DPLL and test structures Cinvestav The chip contains a design of a current mode algorithmic analog to digital converter and some test estructures. Cinvestav The project contains a design of a Digital Phase-Locked Loop Columbia University This chip is a CMOS microarray with integrated CMOS imaging Columbia University elements (photodiodes) below each array site. These elements Columbia University detect the light emitted by flourescently-tagged DNA molecules. Columbia University The chip contained integrated analog-to-digital converters Columbia University which provide a digital output of light intensity at each Columbia University pixel site. Cooper Union University 4 3-bit Flash Analog-to-Digital Converter Cooper Union University 4 Differential Operational Amplifier Cooper Union University 3 adcs and 2 opamps Cooper Union University 4 3-bit ADC's and 6 Op-amps Cooper Union University 7 3bit Flash Analog to Digital Converter Cooper Union University 2 Differential Operational Amplifier Cooper Union University Five 3-bit flash analog to digitial converters. Cooper Union University Four differential operational amplifiers. Cooper Union University 7 ADC, 2 OPAMPS Cooper Union University 4 3-bit Flash ADC's, Cooper Union University 6 Differential Op Amps Cooper Union University 4 3-bit flash ADCs, 6 folded cascode OTAs Cooper Union University 7 ADCs, 2 op amps Cooper Union University Group CX 2001, 7 3 bit ADC and 2 OpAmps Cooper Union University CZ_ADC_2001, 3 bit ADC Cooper Union University 6 ADCs, 3 op amps Cooper Union University ADC and OA for Fred Schade and Farhan Shamsi (Cooper Union) Cornell University Substrate Coupling Measurements. Cornell University Cornell ECE 579 class design project chip 1 - 4 x 4 array of student designs. Cornell University Inductor Coupling Evaluation Cornell University Passive Measurements Cornell University Cornell ECE579 Project Chip 2 Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University Tic Tac Toe Cornell University RISC Processor Cornell University Ethernet monitor Cornell University Stack machine Cornell University 3-Tap filter Cornell University Enigma Cornell University MIPS Processor Cornell University Stack processor Cornell University Media Processor Cornell University RSISC Cornell University Media processor Cornell University IP firewall Cornell University Vector SRAM Cornell University FIR filter Cornell University ATmel-based Processor Cornell University RISC processor Cornell University Data monitor Cornell University Multi-level Memory Cornell University Cache Cornell University RISC processor Cornell University 16-bit processor Cornell University Vector SRAM Cornell University Threshold Logic Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University Fully integrated power amplifier for third generation wideband CDMA Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Fed. Center of Tech. Education of Parana MIN/MAX CMOS FILTER (40-PIN TINY CHIP) George Washington University GAS SENSOR George Washington University FALL00 George Washington University FALL00 George Washington University Mixed Signal George Washington University ADC George Washington University SPRING01 George Washington University Class project #1 George Washington University Class project 2 George Washington University Class project 3 George Washington University Class project 4 George Washington University Class project 5 George Washington University Class project 6 George Washington University Class project 7 George Washington University Class project 8 George Washington University Class project 9 George Washington University Class project 10 George Washington University Gas sensor with circuits interface George Washington University System on Chip Project Georgia Institute of Technology Motoneuron Array with corrected adaptation circuitry- EPots set synaptic weights Georgia Institute of Technology Motoneuron array with new adaptation circuit- no EPots Georgia Institute of Technology Array of tapped calcium circuits with common biases Georgia Institute of Technology HN circuits in 0.5um with Ica output Georgia Institute of Technology HN circuits in 0.5um with Ica output Georgia Institute of Technology Adaptation circuits for VLSI neuron Georgia Institute of Technology Synapse circuits for VLSI neuron Georgia Institute of Technology Single sarcomere to pads Georgia Institute of Technology Single sarcomere to epots Georgia Institute of Technology Silicon Neuron chip with extra calcium output and Georgia Institute of Technology fix for new metal spacing Georgia Institute of Technology Silicon Neuron chip with adjustable sodium slope and Georgia Institute of Technology fix for new metal spacing Georgia Institute of Technology detect synchrony among ensembles of address-event inputs; Georgia Institute of Technology stream data off via fast digital scanner. 1D. Georgia Institute of Technology Ramp ADC for cepstrum. Georgia Institute of Technology Reference test circuits for cepstrum Georgia Institute of Technology New iteration of motoneuron model with EPot synaptic weighting Georgia Institute of Technology Variation on Sarcomere using wide-range amplifiers. Georgia Institute of Technology Synapse circuits for hn neuron Georgia Institute of Technology Adaptation circuits for hn neuron Georgia Institute of Technology Variation on Sarcomere using wide-range amplifiers. Georgia Institute of Technology Revised Analog cepstrum Georgia Institute of Technology Photoarray prototype chip. Georgia Institute of Technology To verify the methodology of designing a VCO for Georgia Institute of Technology GSM application. Georgia Institute of Technology To verify the methodology of designing a quad VCO. Georgia Institute of Technology A study of vector quantization. Contains a classifier array that accepts a Georgia Institute of Technology frequency-domain input signal and tries to match it to one of N possible learned Georgia Institute of Technology signals. The classifier is a two-dimensional array of adaptive and programmable Georgia Institute of Technology amplifiers using differential, floating-gate inputs. The fundamental amplifier is Georgia Institute of Technology the analog counterpart of an XNOR, signaling matching inputs. The array is Georgia Institute of Technology complemented with a row of load circuitry and possibly a winner-take-all circuit Georgia Institute of Technology to process the current output of the array. Georgia Institute of Technology A floating-gate characterization structure. It possesses a p-channel MOSFET with Georgia Institute of Technology its own n-doped well. The gate is floating. It's connected to several input Georgia Institute of Technology capacitors, including one designed for electron tunneling; it is also connected to Georgia Institute of Technology an OTA with negative capacitive feedback, which allows the gate voltage to be Georgia Institute of Technology controlled (through the amplifier's positive input) and the current on and off the Georgia Institute of Technology gate to be measured. The amplifier may also be equipped with reset logic (to Georgia Institute of Technology dissipate or replenish the charge on the floating gate). Georgia Institute of Technology The Cooperative Analog Digital Signal Processing (CADSP) noise suppression Georgia Institute of Technology project seeks to implement a well-explored DSP problem using analog VLSI Georgia Institute of Technology techniques. The goal is to create an analog chip that performs noise Georgia Institute of Technology suppression which equals or exceeds the sound quality produced by a Georgia Institute of Technology digital implementation, with the additional benefits of low power and Georgia Institute of Technology real-time computation. Georgia Institute of Technology Test structures used to collect noise and matching data. Georgia Institute of Technology Band-gap operational amplifier Georgia Institute of Technology Neuron chip with epot structure. Version 2. Georgia Institute of Technology Basic transistor structures. 1st revision. Georgia Institute of Technology Analog computational array for performing speech processing algorithm. Georgia Institute of Technology Analog computational array for performing speech processing algorithm. Georgia Institute of Technology This chip contains several types of continuous-time bandpass filters. Georgia Institute of Technology A chip that mimics the funcition of a dendrite in a neuron. Georgia Institute of Technology This is a simple proof of concept chip. Georgia Institute of Technology A chip that is able to modify itself depending on its inputs. Georgia Institute of Technology This chip has simple feedback and the subcircuits all come out to pins. Georgia Institute of Technology An imager chip using floating gates to do onchip transforamtions. Georgia Institute of Technology A current mode copier chip to store images. Georgia Institute of Technology A second order current mode sigma delta A/D converter chip. Georgia Institute of Technology A chip that is able to modify itself depending on its inputs. Georgia Institute of Technology This chip has simple feedback and the subcircuits all come out to pins. Georgia Institute of Technology This chip has dendritic delays as well and is more complex than chip 2. Georgia Institute of Technology Testing of new structures for non-volitale memeory. Georgia Institute of Technology Including many diffrent structures. Georgia Institute of Technology Testbed for non-volitale systems. This includes many pieces Georgia Institute of Technology to test the whole system including programming structures. Georgia Institute of Technology Neuron chip. 1st revision. No epot structure. Georgia Institute of Technology This chip places differential pair blocks in a programming Georgia Institute of Technology matrix. The programming matrix will enable automatic floating gate Georgia Institute of Technology programming. Georgia Institute of Technology Analog Signal Processing blocks characterization structure. Georgia Institute of Technology A programmable analog array using floating gate technology. Georgia Institute of Technology A 128 by 128 matrix transform chip using floating gates. Georgia Institute of Technology A 16 by 16 matrix transform chip using floating gates. Georgia Institute of Technology A 16 by 16 matrix transform chip using moscaps in the floating gates. Georgia Institute of Technology Self-adapting chip with dendritic delays. There's no feedback. Georgia Institute of Technology Cells can learn and modify itself depending on the input pattern. Georgia Institute of Technology Modified T-gate switches. Wells come out to pins. Proof of concept for new circuit. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Various W/L transistors for providing a noise curve Georgia Institute of Technology Large L transistors carefully laid out for maximum matching Georgia Institute of Technology Photodiode imager with centroid computation and frame differencing. Georgia Institute of Technology Programmable Sigma-Delta A2D using floating gates. Georgia Institute of Technology A noise suppression algorithm implemented as an analog system. Uses bandpass filters and noise and signal estimates to compute a gain per band-limited signal. Georgia Institute of Technology A test chip for the individual elements of a noise suppression system. Georgia Institute of Technology Includes a peak detector, minimum detector, a translinear division circuit, and a gain function/multiplier circuit. Georgia Institute of Technology Series of SOS's with different features. Georgia Institute of Technology This chip will focus on developing an array of second-order continuous-time banpass filters. Georgia Institute of Technology Each element in the array will be programmed with floating gates. Georgia Institute of Technology The overall system will break an input signal into is frequency components. Georgia Institute of Technology This chip contains signal-classification system centered around an array that stores Georgia Institute of Technology signals into one of several quantized vectors by their frequency spectrum. Georgia Institute of Technology test structure for a dense current mode sigma delta array Georgia Institute of Technology an array digital to analog converter using floating gates, also some current mirrors Georgia Institute of Technology an array digital to analog converter using floating gates with a swicth in the input Georgia Institute of Technology This chip has short channel lenght pfet transistors. These Georgia Institute of Technology pfet devices are required for proper operation of the chip. Georgia Institute of Technology This design contains pfet devices with length's smaller than Georgia Institute of Technology the mininum feature length. These short channel devices are Georgia Institute of Technology required for proper operation of the chip. Georgia Institute of Technology Testing of parallel reading of currents on chip. Georgia Institute of Technology This is the 3rd revision of the Neuron chip. Georgia Institute of Technology This contains a floating-gate array. Georgia Institute of Technology There are also several bandpass filters with different ratios of capacitors. Georgia Institute of Technology This is the second version for arrays of bandpass filters. Georgia Institute of Technology There will be two different arrays of thirty-two bandpass second-order Georgia Institute of Technology filters. Each element in both of the arrays will be biased with floating Georgia Institute of Technology gates. Georgia Institute of Technology This chip contains an array of 16 bits D/A converters, and some programing logic. Georgia Institute of Technology A RF chip utilizing a distributed transistor and distributed inductor. Floating-gate elements are used to implement the systems, along with short-channel length transistors. Georgia Institute of Technology This is a 128x128 imager which can be used for performing block transforms on images. Georgia Institute of Technology This is a 48x48 imager to be used for block transforms of images. Floating gates are used to store the different matrix coefficients. Georgia Institute of Technology This is a 16x16 test imager using floating gates. It would be used for motion/ stereo applications. Georgia Institute of Technology The design is NMOS-PMOS power MOSFETs pairs with sensing Georgia Institute of Technology element. The sensing element ratio is 1/100 and is Georgia Institute of Technology located in several points of the die. Georgia Institute of Technology Other test structures are also included. Georgia Institute of Technology NMOS-PMOS Power MOSFETs pair with current-sensing element Georgia Institute of Technology The current sensing ratio in this design is 1/100 and Georgia Institute of Technology it uses the average of 16 sense elements to measure the Georgia Institute of Technology current. The power MOSFETs pair are the essential part Georgia Institute of Technology in DC-DC converter circuits Georgia Institute of Technology NMOS-NMOS and NMOS-PMOS Power MOSFET pairs with sensing Georgia Institute of Technology elements Georgia Institute of Technology The current sensing ratio is 1/1000 in these designs Georgia Institute of Technology and it only includes one current sensing elements. Other Georgia Institute of Technology test structures are also included. Georgia Institute of Technology Design of a high-bandwidth high-capacitive drive op-amp for use in signal processing/filtering Georgia Institute of Technology design comparators Georgia Institute of Technology design a comparator Georgia Institute of Technology design a comparator Georgia Institute of Technology explore the noise property of the MOSFETs Georgia Institute of Technology Structures for high frequency characterization of chip-package interconnects. Georgia Institute of Technology LNA for GSM applications Georgia Institute of Technology LNA for GSM applications Georgia Institute of Technology dc property of the MOSFETs Georgia Institute of Technology dc property of the MOSFETs Georgia Institute of Technology dc testing of the MOSFETs Georgia Institute of Technology on chip inductors Georgia Institute of Technology on chip inductors Georgia Institute of Technology single reduced Hodgkin-Huxley model of a neuron (uses only nap, na, k, and leak conductances) Georgia Institute of Technology nap conductance uses fast activation - next version needs to remove this block Georgia Institute of Technology a continuation of the ver1 design where the ca block has been replaced by another na block (nap conductance) Georgia Institute of Technology test structures using floating gates : multipliers, squaring, summation circuits Georgia Institute of Technology another version of the Hodgkin-Huxley silicon neuron model - Georgia Institute of Technology this version includes a variable slope with the nap conductance Georgia Institute of Technology 12 bit Flash ADC using Floating gate circuits Georgia Institute of Technology Test circuits for (1) high voltage amplifier, (2) translinear divider, (3) autozeroing voltage-to-current peak detector. Georgia Institute of Technology Chip with high voltage epot diff amp, SPI, synapses and dendritic block. Georgia Institute of Technology a continuation of the Hodgkin-Huxley model... Georgia Institute of Technology this version includes three synapses in order to connect other chips Griffith University A small error correcting RAM chip Griffith University Brent Joyce's Pixel Array Griffith University Opi's Pixel Array Griffith University ADC for CMOS Image Sensor designed by Magnus, Satwan & Alok Griffith University CMOS Image Sensor, designed by Group Griffith University Malcolm's Pixel Array Griffith University ALU design used in Design Flow exercise. Griffith University The digital PLL project is done by two postgraduate students, it is a circuit that causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal(generated by an oscillator) with a Griffith University reference or input signal in frequency as well as phase. In the locked state, the phase error between the oscillator's output signal and reference signal is zero or very small. When phase error builds up, a control mechanism acts on the Griffith University oscillator to reduce the error to minimum. In this way, the phase of the output signal is actually locked to the phase of the reference signal. PLL can be regard as a feedback control system. We can analyze PLL by using the method that we Griffith University use to analyze control systems. The chip designed by us is just used for testing. No commercial purpose is expected. Griffith University The Associate Memory project was completed by two post graduate students George and Paul. The data is written into the memory cells which is indicated by the address. Address is generated by the decoder, when it reads, the data comes out Griffith University via tri-state buffer if the tag matches. Griffith University The PLL project is completed by two post graduate students Sijinc and Carlos. The PLL contains, a loop filter and a voltage-controlled oscillator (VCO). The components are connected in the forward path of the loop, while the connection Griffith University between the VCO output and one input of the phase comparator is the feedback path of the system. The frequency range of the PLL is from 20 MHz to 80 MHz. The IC has six terminals: Vdd, Gnd, Input, Output, Filter input and Filter output. Griffith University This project was accomplished by a postgraduate student Aaron. It consists of Griffith University Analog multiplexer Griffith University Temperature compensatated oscillator Harvard University Implementation of an electronic version of the game Othello. Takes inputs for user moves from external buttons and switches and produces outputs to describe the current state of the game for both an LCD display and an LED array Harvard University configuration. Harvard University 16-bit ALU performs ADD, SUBTRACT, AND, ORm XOR, NOT, and 16-by-16 two's-complement signed MULTIPLY. Standard process is four steps: load first input, load second input, calculate, and write output. Calculate is one cycle for all but the Harvard University MULTIPLY, which has a 16-cycle calculation step. MULTIPLY also requires an extra cycle at the end to read the second 16 bits of the output. Harvard University Implementation of a pulse-width encoder/transmitter and decoder/receiver in a MOSIS TinyChip padframe. Harvard University Implementation os an office or household lighting and applicance control unit for energy savings and for safety purposes in a 1.5um MOSIS TinyChip SCMOS lambda=0.8um. Harvey Mudd College multiple student projects: adders, FSMs Harvey Mudd College An asynchronous FIFO chip designed by eight freshmen. Harvey Mudd College Array multiplier from VLSI class ported to AMI 0.5m process with new pads Harvey Mudd College freshman bit error rate tester chip Harvey Mudd College Class project Harvey Mudd College Hangman game Harvey Mudd College includes ROM Harvey Mudd College Class project Harvey Mudd College FIR filter Harvey Mudd College Class project Harvey Mudd College Booth-encoded multiplier Illinois Institute of Technology Modified Newton Raphson Divison, Array Multiplier and ALU Illinois Institute of Technology PowerALU Project, ADD/SUB/DIV ALU class project ECE 429 Illinois Institute of Technology 8 bit ALU class project ECE429, Add, Sub, Newton Raphson Divide, Reciprocal Illinois Institute of Technology ECE429 Term project: newton raphson divison and ALU functions. Iowa State University The aim of this project is to design a Bandpass Sigma Delta modulator for Iowa State University use in the baseband block of a Wideband Code Division Multiple Access (WCDMA) Iowa State University down conversion receiver. Iowa State University This project is about characterization of several types of rf transformers including center tapped and toroidal solenoids. S parameters will be extracted for the 3 port and 4 port transformers and 2 port inductors. It also has several PMOS Iowa State University and NMOS rf devices. Iowa State University This project explores the impacts of two passive RF components: an inter-stage inductor and a gate parallel capacitor, on the performance of an inductor-load cascoded common source low noise amplifier with inductive degeneration with Iowa State University various configurations and sizes through design, simulation, fabrication, testing, and characterization. Iowa State University LNA 5 G, 802.lla Johns Hopkins University operational transconductance amplifiers Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University operational transconductance amplifiers Johns Hopkins University support vector test machine chip, computational rows Johns Hopkins University adaptive filter chip Johns Hopkins University operational transconductance amplifiers Johns Hopkins University 40x40 pixel beam width metric and centroid imager Johns Hopkins University operational transconductance amplifiers Johns Hopkins University floating-gate dosimeter study Johns Hopkins University Floating gate kernels Johns Hopkins University design with everything Johns Hopkins University support vector small version, no ADC Johns Hopkins University delta-sigma plus svm, class project 2x2 tiny Johns Hopkins University delta sigma with feedback Johns Hopkins University Stereo circuit test Johns Hopkins University Address-Event Retina Chip Johns Hopkins University Isolation amplifier and Tx modules Johns Hopkins University ratio spectrum chip Johns Hopkins University Chip contains photodetector array and motion cells. Image and Optical flow field is scanned out. Johns Hopkins University potentiostat plus delta-sigma A/D Johns Hopkins University potentiostat plus delta-sigma A/D Johns Hopkins University Transistor matching test array Johns Hopkins University Transistor matching test array Johns Hopkins University A dense array of BJT pixels. Johns Hopkins University Polymer Imager and Tx modules Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University potentiostat plus telemetry Johns Hopkins University potentiostat with delta-sigma A/D Johns Hopkins University Bit-Matrix transpose DRAM Johns Hopkins University Current reference and other test structures Johns Hopkins University Support Vector Machine with forward decoding Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University Capacitive sensor circuit for capacitive sensors. Johns Hopkins University digital multiplier Johns Hopkins University student project: car alarm controller Johns Hopkins University Digital portion of Direct Digital Synthesizer Johns Hopkins University Detector Array for controlling a Deformable Mirror Johns Hopkins University Multi-channel potentiostat with revised clocking Johns Hopkins University Real-time laser beam width metric chip for adaptive optics Johns Hopkins University Acoustic signal processing system with wakeup detector and sound localization circuits Johns Hopkins University Pressure sensor transmitter Johns Hopkins University Alternate pressure sensor Johns Hopkins University Regulator,oscillator,ota,reference Lafayette College WimpNet (simplified Ethernet) receiver. Lafayette College A network transmitter interface for a simple protocol called "WimpNet" which uses collision detection. Lafayette College Network transmitter interface for a simple protocol called WimpNet. Lafayette College Receiver interface for simple network protocol "WimpNet". Lafayette College Transmitter interface circuit for "WimpNet" - simple ethernet-like network protocol. Lafayette College Half-bridge to connect together two "WimpNet" (simplified ethernet) networks together - forwards packets from one net to another. Lafayette College 4-bit successive approximation A/D converter based on voltage-scaling DAC Lafayette College 4-bit Successive-Approximation A/D Converter Lafayette College 4-bit successive approximation A/D Converter Lafayette College 4-bit successive approximation A/D converter Lafayette College 4-bit succ. approximation A/D converter Lafayette College 4-bit successive approximation A/D converter Louisiana State University CMOS VLSI IMPLEMENTATION OF 4-BIT MAGNITUDE Louisiana State University COMPARATORS (2-DESIGNS) Louisiana State University CMOS IMPLEMENTATION OF 4-BIT COUNTERS: Louisiana State University RIPPLE COUNTER, BCD COUNTER, BINARY COUNTER Louisiana State University CMOS VLSI IMPLEMENTATION OF 4-BIT Louisiana State University BIDIRECTIONAL SHIFT-REGISTERS Louisiana State University VLSI IMPLEMENTATION OF A TERNARY-TO-BINARY Louisiana State University LOGIC CONVERSION IN FLOATING GATE MOSFET CMOS Louisiana State University CIRCUIT DESIGN Louisiana State University VLSI IMPLEMENTATION OF A 10-BIT DAC IN CHARGE Louisiana State University SCALING ARCHITECTURE. THE DESIGN INCLUDES TEST Louisiana State University CIRCUITS. Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT ALU IN Louisiana State University FLOATING GATE MOSFETS. THE DESIGN INCLUDES Louisiana State University TEST DEVICES. Louisiana State University VLSI IMPLEMENTATION OF TERNARY TO BINARY LOGIC Louisiana State University DIGITAL CIRCUITS. THE DESIGN ALSO INCLUDES TEST Louisiana State University DEVICES. Louisiana State University VLSI IMPLEMENTATION OF THREE DIFFERENT TYPES OF Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT ALU. THE DESIGN Louisiana State University INCLUDES 4_LOGIC AND 4-ARITHMETIC OPERATIONS. Louisiana State University VLSI IMPLEMENTATION OF A BCD-TO-SEVEN Louisiana State University SEGMENT CONVERTER DESIGN Louisiana State University VLSI IMPLEMENTATION OF TWO 4-BIT COUNTERS- Louisiana State University SYNCHRONOUS COUNTER AND COUNTER WITH PARALLEL Louisiana State University LOADS Louisiana State University VLSI IMPLEMENTATION OF TWO 4-BIT COUNTERS: Louisiana State University BCD RIPPLE COUNTER AND A BINARY COUNTER Louisiana State University VLSI IMPLEMENTATION OF THREE TYPES OF 4-BIT Louisiana State University SHIFT REGISTERS: SERIAL-TO-PARALLE, PARALLEL-TO Louisiana State University -SERIAL AND BIDIRECTIONAL TYPES Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT BINARY COUNTER Louisiana State University WITH PARALLEL LOAD AND A BCD RIPPLE COUNTER Louisiana State University VLSI IMPLEMENTATION OF AN AMPLIFIER IN Louisiana State University CMOS TECHNOLOGY. THE DESIGN ALSO INCLUDES Louisiana State University A SIMPLE TEST INVERTER. Michigan State University This integrated circuit contains a 3-bit counter, a 2-bit ripple-carry adder, a 2-bit pipeline, three inverters of different b values, two ring-oscillators (one standard, one custom) three NMOS transistors, two NOR gates, two NAND gates, Michigan State University two resistors of different sizes, an XOR gate, an XNOR gate, a 4-input OR, a 4-input multiplexer, a tristate buffer, a 4-input AND, a Schmitt Trigger, a transmission gate, an AND/OR invert, a transmission gate XOR, a D flip-flop, a 3-input Michigan State University XOR, a PDN-PUN transmission gate as well as five useful custom logic functions: AB+C, (A+B)C, AB+AC, A’B’C, and ( ).. The contact person is Ellen McKenzie (mckenz33@egr.msu.edu). Michigan State University This integrated circuit contains two 2-Input NAND Gates, two 2-Input NOR Gates, 2 ring oscillators, 2 to 1 Selector as a combinatorial circuit, a 2 to 1 selector as a pipeline circuit, 3 NMOSs, 2 resistors, 3 Inverters of different betas, Michigan State University and a 2-Bit up down counter as a sequential logic circuit. The contact person is Nathan Dotson (dotsonna@pilot.msu.edu) Michigan State University This integrated circuit contains following: 2 ring oscillators, 3 PMOS transistors, 3 CMOS inverters, 2 Resistors, 2 NOR gates, 2 NAND gates, MOD 4 counter, 2 bit adder, and Pipeline circuit. The contact person is Bradley Michigan State University Wynn(wynnbrad@pilot.msu.edu). Michigan State University This circuit contains: 3 NMOS transistors, 3 CMOS inverters, 2 ring oscillators, 2 resistors, 1 four-bit counter, a combinatorial logic circuit, a pipeline logic circuit and the following gates: 2 NOR, 2 NAND, X'Y, Y'X, 4NOR, 4NAND, 3NOR, Michigan State University 3NAND, 3OR, XOR, OR. The contact person is Scott Cogan Michigan State University This circuit contains 3 PMOS transistors, 3 CMOS inverters, 2 ring oscillators, 2 resistors, 2 NOR Gates, 2 NAND gates, a Modulo-4 counter, a combinatorial version two-bit full-adder, a pipeline version two-bit full-adder, and ten unique Michigan State University logic gates. The contact person is Mark Szymczak (szymcza4@msu.edu) Michigan State University This Circuit Contains three NMOS transistors, three CMOS inverters, two NOR gates, two NAND gates, two 75-MHz ring oscillators, 5K Ohm resistor, 50K Ohm resistor, NORC (OR/NOR) gate, two-to-one MUX, three-input NOR gate, three-input NAND Michigan State University gate, 2-Bit Ripple-Carry Adder, 2-Bit Ripple-Carry Adder (Pipeline Implemenatation) and a modul0-4 counter. The Contact Person Is Pedro Barba (barba@msu.edu). Michigan State University This integrated circuit design is a compilation of compilation of devices of various size and complexity. Included are transistors, a wide variety of digital logic gates, ring-oscillators, resistors, (2) 8-bit selectors, and a 3 bit Michigan State University counter. Project Contact: Cory La Count lacountc@msu.edu. Michigan State University Our project contains the following (1) 3 PMOS transistors; (2) 3 CMOS inverters; (3) 2 CMOS NAND gates; (4) 2 CMOS NOR gates; (5) 2 75MHz Ring Oscillators; (6) 1 2-input XOR gate; (7) 1 2-input OR gate; (8) 1 4to1 Multiplexer; (9) Michigan State University 1 Buffer; (10) 1 2-input AND gate; (11) 1 3-input AND gate; (12) 1 2-bit counter; (13) 1 2-bit ripple-carry adder; (14) 1 4-input NAND gate; and (15) 1 4-input NOR gate. Contact Information--Andrew Held email: heldandr@msu.edu. Michigan State University This integrated circuit contains 2 ring oscillators, 2 NANDS, 2 NORS, 3 Inverters, The contact person is Ryan Amman (ammanrya@egr.msu.edu). Michigan State University This integrated circuit contains 2 NAND Gates, 2 NOR Gates, Three PMOS transistors, 2 Ring Oscillators, 3 Inverters, 8 standard cell Logic Gates, and a Microprocessor including eight functions, a Pipeline Adder, a Combinatorial Adder, an Michigan State University Arithmetic Shift Left, an Arithmetic Shift Right, Increment, a Two's Complement, a Compare function, and a Bitwise XNOR. Michigan State University This integrated circuit contains 3 inverters, CMOS NOR, NAND and XOR gates, a pseudo-NMOS XOR gate, two ring oscillators, a MOD5 counter and a One's Counter. The contact person is David Bordoley (bordoley@msu.edu) Michigan State University This project is the final project for ECE410. We built a chip containing a 8 bit comparator, a tail light, a nor gate, a nand gate, a CMOS xnor gate, a Pseudo Xnor gate, three different inverters, and two ring oscillators with varied Michigan State University frequency. Contact person Cecilia Richardson email address:richa186@egr.msu.edu Michigan State University This circuit contains three variable size inverters, 2 ring oscillators, 8-bit comparator, 4-bit shift register, 4 to 1 multiplexor, NAND Gate, NOR Gate and 2 XOR Gates. The contact person is Jacob Alamat (alamatja@egr.msu.edu). Michigan State University This integrated circuit contains 3 inverters of differing P-N Ratios, 2 Ring Oscillators, 1 NAND gate, 1 NOR gate, 1 CMOS XOR Gate, 1 Pseudo-NMOS XOR Gate, a 2-bit Adder/Subtracter, and a taillight controller for a Ford Thunderbird. The Michigan State University contact person is Jeffrey Blank (blankjef@msu.edu). Michigan State University This integrated circuit contains three inverters, a NOR and a NAND gate, a static CMOS technology and a Pseudo-NMOS technology XOR gate, two ring oscillators, a four-bit full adder, and an automotive taillight controller. The contact Michigan State University person is John Lee (leejohn2@egr.msu.edu). Michigan State University This chip contains contains 3 inverters, two ring oscillators, a Xor using Cmos, a Xor using Pseudo-Nmos, a Nand, a Nor, a Mod-8 up and Down Counter and a 4-bit full adder/subtrator. The contact person for design team #7 of spring '01 Michigan State University would be Erich Dams his email is Damseric@msu.edu. Michigan State University This integrated circuit contains an 8 bit A/D converter, three inverters, Pseudo-NMOS and CMOS XOR gates, and two ring oscillators. The contact person is Joshua Schwannecke(schwanne@msu.edu). Michigan State University This integrated circuit contains three custom inverters, two ring oscillators, a 2-input NAND gate, a 2-input NOR gate, a CMOS 2-input XNOR gate, a pseudo-NMOS 2-input (and a bias) XNOR gate, and a 512-bit SRAM memory block. The contact Michigan State University person is Brian McCarthy (mccart85@msu.edu). Michigan State University This integrated circuit contains 3 inverters, a NAND gate, a NOR Gate, a CMOS XNOR gate, a pseudo-NMOS XNOR Gate, two ring oscillators, and 256 bits of SRAM. The contact person is P. D. Fisher (fisher@egr.msu.edu). Michigan State University This integrated circuit contains a four-bit ALU, three inverters, a CMOS NAND gate, a CMOS NOR gate, a CMOS XNOR gate, a pseudo-NMOS XNOR gate, two ring oscillators, and a 4-bit mod12 binary counter. The contact person is Garrett Heraty Michigan State University (heratyga@egr.msu.edu). Michigan State University ECE 410 design team 4 ASIC. This chip contains 2 input NAND, NOR, CMOS XOR and Pseudo NMOS XOR gates. It also has 3 inverters, 2 ring oscillators, a 4-1 digital mux, 3 bit binary counter and a 3-bit adder. Contact Samir Patel Michigan State University . Michigan State University The IC contains several gates, two ring oscillators, a 4-bit up counter, and a 4-bit Conditional Sum Adder. The contact person is Lonnie Halash (halashlo@msu.edu) Michigan State University This integrated circuit contains three inverters, two ring oscillators, two XNOR gates, an 8 to 1 multiplexor, one NAND gate, one NOR gate and a 2-bit binary counter. The contact person is Carl J. Denslow (denslowc@msu.edu). Michigan State University The chip contains three custom inverters, five standard cells (NOR, NAND, CMOS XOR, 4-input OR and Pseudo NMOS XOR), two ring oscillators, a 2-bit adder and a 4-bit counter. Michigan State University This integrated circuit contains an SRAM memory cell, and a test circuit with several small components (inverters, ring oscillator, etc). The contact person is Chris Wozniak (woznia13@msu.edu). Michigan State University This integrated circuit contains full memory block, consisting of a read/write circuit, a controller/decoder, and a SRAM memory core. Contact person is Jim Block at blockja1@msu.edu. Michigan State University This integrated circuit contains three CMOS inverters, one CMOS NOR gate, one CMOS XNOR gate, one pseudo-NMOS XOR gate, two ring oscillators, one four-bit adder/subtractor, one three bit multiplier/divider, and one four-bit binary counter Michigan State University mod-14. The contact person for out group is Dave Warren (warrend5@msu.edu). Michigan State University 8x8 SRAM Memory Core, Row Decoder, Read Write Circuit, and Controller. The contact person is Andrew Deacon (deaconan@msu.edu). Michigan State University This integrated circuit contains three inverters with different P/N ratios, 2 ring oscillators, 2 input NAND gate, 2 input NOR gate, 2 input CMOS XNOR gate, 2 input Pseudo-NMOS XNOR gate, NMOS transistor, 3-Bit decoder, 3-Bit up/down Michigan State University counter. The contact person is zhonghua li (lizhongh@msu.edu). Mississippi State University Interface between DS1620 temperature sensing chip and seven segment LED display. ALso includes other simple functions. Mississippi State University digital padframe testchip Mississippi State University DDFS test structure 2560L 25P 22S Mississippi State University DDFS test structure 2560L 10P 22S Mississippi State University DDFS test structure 2560L 5P 22S Mississippi State University This design is a set of chargepumps and OTAs for proof tests that are needed for an analog IC design class. Mississippi State University initial prototype of 16 bit accumulator with phase detection logic Mississippi State University plus initial prototype of voltage follower based on OTA Mississippi State University revised ROM-less direct digital frequency synthesizer Mississippi State University 2nd generation current mode flash ADC Naval Postgraduate School Programmable GICT switch capacitor filter. Naval Postgraduate School Eight-bit, fast, full carry lookahead adder. New Mexico State University Class AB Op Amp by Carlos Nieva New Mexico State University Fast Op Amp by Mike Holmes New Mexico State University Proto-typing CMOS subcircuits New Mexico State University Proto-typing CMOS subcircuits New Mexico State University Digital Test Chip New Mexico State University This Project will fabricate Analog Adaptive Median Filters. New Mexico State University Inductors/Transformers of various styles, metals, and layout configurations wiil be fabricated. New Mexico State University Digital logic gates to implement Boolean functions New Mexico State University with charge pump and voltage regulator. The functions New Mexico State University are AND, XOR, and a DFF. Different logic styles are New Mexico State University used: static CMOS, CVSL, Pass Transistor Logic, and New Mexico State University Dynamic Logic New Mexico State University This project will fabricate a Multiple Input Linear Weighted Differential Amplifier. New Mexico State University This Project will fabricate a 15th order Rank Order Filter with output selection circuitry. New Mexico State University This project will fabricate a Class AB Op Amp for low voltage applications and a low voltage multiplier. New Mexico State University This project will fabricate test circuitry. New Mexico State University This chip contains two new OTA designs and two configurations for a new low voltage analog mixer. New Mexico State University New OTA Design New Mexico State University This chip contains several new Current Source Designs New Mexico State University This chip contains a new, low voltage, two stage, class AB opamp design. New Mexico State University Nodal analysis Vddq with OTA as circuit under test. New Mexico State University This Chip contains several new Analog Multiplier Designs. New Mexico State University This chip contains several new Analog Multiplier Designs. New Mexico State University This Chip contains several inverter gain stages. New Mexico State University This chip contains a fully differential analog multiplier design. New Mexico State University Rank Order Filter that has new digital circuitry to select specific ranks and allow for better testing control of circuitry. New Mexico State University Testing circuit for floating gate MOSFETS. New Mexico State University Differential Multiple Input Linear Differential Amplifier. New Mexico State University This chip contains 4 Quadrant Multiplier circuits with floating gates. New Mexico State University High Frequency Feed Through Amplifier New Mexico State University High Speed Dynamic Current Sensor New Mexico State University Several configurations of a proposed OTA will be fabricated including a new fully differential version. New Mexico State University Several OTA implementations will be fabricated with Lateral PNP transistors. The chip also contains a single Lateral PNP for characterization. New Mexico State University Rank order filter with four inputs and Current mirrors floating substrate Ohio State University Limter with RSSI Version 1 Ohio State University LPF1 and LPF2 Ohio State University LPF3 and LPF4 Ohio State University HPF1 and HPF2 Ohio State University HPF3 and Attenuator Ohio State University fully differential CCII Ohio State University MOSFET-C Filter Ohio State University MOSFET-C Low Pass Filter Ohio State University Limter with RSSI Version 2 Ohio State University A fully integrated frequency mixer Ohio State University A fully integrated voltage controlled oscillator Ohio State University A bonding diagram has been faxed to you. Ohio State University Please make note of it and let Ohio State University us know wheter you get the fax or not. Ohio State University The Nemesis chip implements the Nemesis Encryption algorithm Ohio State University 5 Bit SAR ADC Ohio State University RF-ID clock and vdd generation Ohio State University low pass filters Ohio State University low pass filters Ohio State University high pass filters Ohio State University High pass filters Ohio State University buffer and attenuator Ohio State University Programmable RSSI Ckt Ohio State University 4-20mA Receiver and 2nd-Order Delta-Sigma Modulator with Ohio State University test opamps and voltage bais circuits Ohio State University The section of the Nautilus chipset is the bare SPI unit Ohio State University that is able to transmit and receive serial bits in a recirculating Ohio State University fashion. Ohio State University This section of the Nautilus chipset provides the Ohio State University decimation and noise shaping of the DSM2's pulse density stream. Ohio State University The part of the Nautilus chipset is the SPI internal Ohio State University latching mechanism necessary for implementing a full scale SPI Ohio State University interface. Ohio State University This is an experimental second order decimation filter Ohio State University that converts a pulse density stream into a 16-bit word. Decimation Ohio State University gain and length are programmable. Ohio State University 4-bit Flash ADC Ohio State University PLL Design 1 Ohio State University PLL Design 2 Ohio State University CMOS EEPROM Design Ohio State University Sonnet Serializer group Ohio State University CAM Design 1 Ohio State University CAM Design 2 Ohio State University Differential Opamp Bias Circuitry Ohio State University Fully Differential Fourth-Order Delta-Sigma Modulator A/D Ohio State University This chip implements the Nemesis encryption algorithm Ohio State University CAM Design 1 Ohio State University CAM Design 2 Ohio State University Flash ADC 4 Bit Ohio State University PLL Design 1 Ohio State University PLL Design 2 Ohio State University complete RSSI circuit Ohio State University SAR ADC 6-bit Ohio State University SONNET Serializer Circuit Ohio State University Wavelet DSP core Ohio State University oscillator for 2.4 GHz Oregon Graduate Institute This is an opamp and a buffer with two inverters. I would like you to fabricate the layout design only on the packaged part, not on the unpackaged parts. Oregon Institute of Technology analog&digital experiments Prairie View A&M University lan hu's comparator chip Prairie View A&M University 3x* DECODER WITH A 5 STAGE CASCADING INVERTER PROJECT DESIGN FOR ELEG 5173 Prairie View A&M University 2 x 4 decoder with enable Princeton University This project is a class project for ELE462 at Princeton University. It is an enhanced DES encryption chip in the sense that both SBOX and PBOX can be programmed. The chip is designed with Cadence tools using NCSU package. Princeton University This is the second chip we are going to fabricate for the spring semester 2001. Purdue University leakage controlled 4k SRAM Queens University of Belfast Two 5.5 GHz amplifiers, standard and linearised Rice University The PRIME chip implements an optimized trial-division method to verify the Rice University primality of an 8-bit unsigned integer input. It uses a ring counter to Rice University exploit the "prime jumping" sequence, significantly reducing the number of Rice University trial divisors that must be tested. It asserts an output signal PRIME Rice University when testing is done if the number has no factors. Rice University ATMCNTRL is the control chip for an ATM machine. The ATM will allow a Rice University manager to add/delete user accounts while the user will have standard ATM Rice University options to choose from. These options include: withdrawal, deposit, and Rice University checking the balance. This chip will interface with the ATM I/O chip. Rice University It is designed to compute the discrete wavelet transform coefficients in a Rice University cascaded FIR style. With simplified algorithm design, we use only one Rice University multiplier and accumulator and some in-chip memory controlled by several Rice University PLAs to get the coefficients {C} and {D} with desired precision.These Rice University coefficients are very useful for applications. Rice University GAMBLER1 implememts a simplified form of the popular casino game Rice University Blackjack. Four inputs from the player control the deal of a hand, a hit, Rice University a stay, and the restart of a game. Player total, computer total, the most Rice University recently dealt "card", and the possible outcomes are displayed as outputs. Rice University The GCF chip calculates the greatest common factor of two 6-bit unsigned Rice University inputs. The output is a 6-bit unsigned integer which represents the Rice University greatest common factor of the two inputs. The chip consists of adders, Rice University programmable logic arrays, and shift registers to perform several divide Rice University and multiply operations. Rice University A (4/8) Hamming encoder/decoder pair. Takes a 4-bit input and Rice University encodes it with error-correcting code, allowing the decoder to check and Rice University correct single-bit errors as well as detect and indicate when double-bit Rice University errors have occured. Provides fault-tolerant data transfer. Rice University This chip performs pipelined detection for WCDMA. First, correlation Rice University matrices and 8-bit soft decisions for each of 5 users are loaded. One-bit Rice University hard decisions representing the past, present and future are used with the Rice University correlation matrices to produce a better hard decision for use by later Rice University pipeline stages. Rice University This chip implements the IDEA encryption algorithm. The chip Rice University takes a 4-bit round number, a 16-bit data block, and a 32-bit key. Rice University The chip executes a series of mathematical operations for the Rice University specified number of rounds. When the last round is Rice University completed, the final 16-bit output of the chip is produced. Rice University Efficient detection and Error correction is of utmost importance Rice University in modern communication. The Viterbi Decoding algorithm is a elegant and Rice University powerful approach in this area. Our Chip implements a rate 1/2 Viterbi Rice University decoder with a traceback depth of 16. The operational clock frequency is Rice University 4.54 Mhz and the maximum input data rate is 94.6 kilobits/second. Rice University ALCOHOL implements a human blood alcohol content calculator. Based on the Rice University type of drink, number of drinks, weight and number of hours drinking, our Rice University chip computes an individual's BAC. Registers store the inputs. Configured in Rice University an accumulator-style, the chip uses an adder (16-bit) and shift register Rice University (32-bit) for computation. Rice University This chip is an instruction scheduler. It operates on a simple 8-long Rice University block of 8-bit instructions, which are found in off-chip memory. The chip Rice University determines which instructions can and should be reordered, using our Rice University dependency and reordering algorithms, and then reorders them in the Rice University off-chip memory. Rice University Our project tries to implement an addtion and subtraction Rice University algorithm in a family of algorithms called Online Arithmetic. It is designed Rice University to do mathematical operations in the unconventional way of MSB to LSB. Rice University This chip processes sixteen by sixteen eight bit grayscale images. It can Rice University perform one of six different functions: inversion, flip horizontally, Rice University flip vertically, smooth by minimum, smooth by maximum, or smooth by Rice University average. Both the source and output images are stored in external memory. Rice University The chip implements the ADPCM voice encoding algorithm. Rice University It encodes 16-bit voice data input stream into 4-bit data Rice University output stream. Necessary control signals are provided to Rice University interface the chip with supporting system to form a Rice University real-time voice encoder. Rice University The Decimal to Fraction Converter takes in a 3-digit decimal number Rice University between 0 to 1. The greatest common factor (GCF) is found for the Rice University input and the number 1000. The numerator (input) and denominator (1000) Rice University are divided by the GCF. The results are outputted as integers Rice University to represent the fraction. Rice University Our project is working with another group to develop a two-chip ATM Rice University controller system. Our chip will be more of a "front end" in the system, Rice University