Report generated: 27-Jun-2002 ORGANIZATION DESCRIPTION ---------------------------------------- --------------------------------------------------- Alfred University misc analog parts Assiut University This project is student project and has been approved by MOSIS Educational Program (MEP).The account name : Assiut University ACCOUNT name : 3180-MEP-INS/ASSIUTU-EE Boise State University francis's chip Boise State University kegan's chip Boise State University curtis' chip Boise State University a chip Boise State University a chip Boise State University Jose's chip Boise State University tim's chip Boise State University scott's chip Boise State University r-2r chip Boise State University schottky diodes Boise State University Schottky diode test structurs for EE515 Boise State University CMOS filter Boise State University test structures Boise State University analog test structures Boise State University Bill's chip with test structures Boise State University chip1 from Spring 2002 EE410 Boise State University chip2 from Spring 2002 EE410 Boise State University chip3 from Spring 2002 EE410 Boise State University chip4 from Spring 2002 EE410 Boise State University chip5 from Spring 2002 EE410 Boise State University chip6 from Spring 2002 EE410 Boise State University chip7 from Spring 2002 EE410 Brigham Young University cameron_wilde's ECE 451/445 class project Brigham Young University ben_stevenson's ECE 451 class project Brigham Young University bryant_smith's ECE 451 class project Brigham Young University don_bigler's ECE 451 class project Brigham Young University jacob_evans's ECE 451 class project Brigham Young University kevin_harper's ECE 451 class project Brigham Young University mary_sanders's ECE 451 class project Brigham Young University travis_williams's ECE 451 class project Brigham Young University rick_demille's ECE 451 class project Brigham Young University james_davis's ECE 451 class project Brigham Young University nathan_reynolds's ECE 451 class project Brigham Young University brian and emy lefevre's project Brigham Young University ben_johnson's ECE 451 class project Brigham Young University benjamin_wright's ECE 451 class project Brigham Young University brandon_langford's ECE 451 class project Brigham Young University jeff_bowden's ECE 451 class project Brigham Young University dan_carver's ECE 451 class project Brigham Young University justin_fitzpatrick's ECE 451 class project Brigham Young University joshua_parker's ECE 451 class project Brigham Young University randon_richards's ECE 451 class project Brown University This chip contains control and sequence logic for a system that will provide amplification/multiplexing of neural signals in a low power array sensor. The control is implemented in dynamic logic and this first step is to be sure that power Brown University and speed can be met while preparing for a later more integrated system. California State University Northridge digital game circuits California State University Northridge more games California State University Northridge signal gen. California State University Sacramento Four independent voltage-to-frequency converters Cinvestav The project contains a design of a switched-current sigma-delta modulator and some test structures Cinvestav The project contains a design of a DPLL and test structures Cinvestav The chip contains a design of a current mode algorithmic analog to digital converter and some test estructures. Cinvestav The project contains a design of a Digital Phase-Locked Loop Columbia University This chip is a CMOS microarray with integrated CMOS imaging Columbia University elements (photodiodes) below each array site. These elements Columbia University detect the light emitted by flourescently-tagged DNA molecules. Columbia University The chip contained integrated analog-to-digital converters Columbia University which provide a digital output of light intensity at each Columbia University pixel site. Cooper Union University 4 3-bit Flash Analog-to-Digital Converter Cooper Union University 4 Differential Operational Amplifier Cooper Union University 3 adcs and 2 opamps Cooper Union University 4 3-bit ADC's and 6 Op-amps Cooper Union University 7 3bit Flash Analog to Digital Converter Cooper Union University 2 Differential Operational Amplifier Cooper Union University Five 3-bit flash analog to digitial converters. Cooper Union University Four differential operational amplifiers. Cooper Union University 7 ADC, 2 OPAMPS Cooper Union University 4 3-bit Flash ADC's, Cooper Union University 6 Differential Op Amps Cooper Union University 4 3-bit flash ADCs, 6 folded cascode OTAs Cooper Union University 7 ADCs, 2 op amps Cooper Union University Group CX 2001, 7 3 bit ADC and 2 OpAmps Cooper Union University CZ_ADC_2001, 3 bit ADC Cooper Union University 6 ADCs, 3 op amps Cooper Union University ADC and OA for Fred Schade and Farhan Shamsi (Cooper Union) Cornell University Substrate Coupling Measurements. Cornell University Cornell ECE 579 class design project chip 1 - 4 x 4 array of student designs. Cornell University Inductor Coupling Evaluation Cornell University Passive Measurements Cornell University Cornell ECE579 Project Chip 2 Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University Tic Tac Toe Cornell University RISC Processor Cornell University Ethernet monitor Cornell University Stack machine Cornell University 3-Tap filter Cornell University Enigma Cornell University MIPS Processor Cornell University Stack processor Cornell University Media Processor Cornell University RSISC Cornell University Media processor Cornell University IP firewall Cornell University Vector SRAM Cornell University FIR filter Cornell University ATmel-based Processor Cornell University RISC processor Cornell University Data monitor Cornell University Multi-level Memory Cornell University Cache Cornell University RISC processor Cornell University 16-bit processor Cornell University Vector SRAM Cornell University Threshold Logic Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Cornell University Fully integrated power amplifier for third generation wideband CDMA Cornell University A project chip for ECE 493. Cornell University A project chip for ECE 493. Fed. Center of Tech. Education of Parana MIN/MAX CMOS FILTER (40-PIN TINY CHIP) George Washington University GAS SENSOR George Washington University FALL00 George Washington University FALL00 George Washington University Mixed Signal George Washington University ADC George Washington University SPRING01 George Washington University Class project #1 George Washington University Class project 2 George Washington University Class project 3 George Washington University Class project 4 George Washington University Class project 5 George Washington University Class project 6 George Washington University Class project 7 George Washington University Class project 8 George Washington University Class project 9 George Washington University Class project 10 George Washington University Gas sensor with circuits interface George Washington University System on Chip Project Georgia Institute of Technology Motoneuron Array with corrected adaptation circuitry- EPots set synaptic weights Georgia Institute of Technology Motoneuron array with new adaptation circuit- no EPots Georgia Institute of Technology Array of tapped calcium circuits with common biases Georgia Institute of Technology HN circuits in 0.5um with Ica output Georgia Institute of Technology HN circuits in 0.5um with Ica output Georgia Institute of Technology Adaptation circuits for VLSI neuron Georgia Institute of Technology Synapse circuits for VLSI neuron Georgia Institute of Technology Single sarcomere to pads Georgia Institute of Technology Single sarcomere to epots Georgia Institute of Technology Silicon Neuron chip with extra calcium output and Georgia Institute of Technology fix for new metal spacing Georgia Institute of Technology Silicon Neuron chip with adjustable sodium slope and Georgia Institute of Technology fix for new metal spacing Georgia Institute of Technology detect synchrony among ensembles of address-event inputs; Georgia Institute of Technology stream data off via fast digital scanner. 1D. Georgia Institute of Technology Ramp ADC for cepstrum. Georgia Institute of Technology Reference test circuits for cepstrum Georgia Institute of Technology New iteration of motoneuron model with EPot synaptic weighting Georgia Institute of Technology Variation on Sarcomere using wide-range amplifiers. Georgia Institute of Technology Synapse circuits for hn neuron Georgia Institute of Technology Adaptation circuits for hn neuron Georgia Institute of Technology Variation on Sarcomere using wide-range amplifiers. Georgia Institute of Technology Revised Analog cepstrum Georgia Institute of Technology Photoarray prototype chip. Georgia Institute of Technology To verify the methodology of designing a VCO for Georgia Institute of Technology GSM application. Georgia Institute of Technology To verify the methodology of designing a quad VCO. Georgia Institute of Technology A study of vector quantization. Contains a classifier array that accepts a Georgia Institute of Technology frequency-domain input signal and tries to match it to one of N possible learned Georgia Institute of Technology signals. The classifier is a two-dimensional array of adaptive and programmable Georgia Institute of Technology amplifiers using differential, floating-gate inputs. The fundamental amplifier is Georgia Institute of Technology the analog counterpart of an XNOR, signaling matching inputs. The array is Georgia Institute of Technology complemented with a row of load circuitry and possibly a winner-take-all circuit Georgia Institute of Technology to process the current output of the array. Georgia Institute of Technology A floating-gate characterization structure. It possesses a p-channel MOSFET with Georgia Institute of Technology its own n-doped well. The gate is floating. It's connected to several input Georgia Institute of Technology capacitors, including one designed for electron tunneling; it is also connected to Georgia Institute of Technology an OTA with negative capacitive feedback, which allows the gate voltage to be Georgia Institute of Technology controlled (through the amplifier's positive input) and the current on and off the Georgia Institute of Technology gate to be measured. The amplifier may also be equipped with reset logic (to Georgia Institute of Technology dissipate or replenish the charge on the floating gate). Georgia Institute of Technology The Cooperative Analog Digital Signal Processing (CADSP) noise suppression Georgia Institute of Technology project seeks to implement a well-explored DSP problem using analog VLSI Georgia Institute of Technology techniques. The goal is to create an analog chip that performs noise Georgia Institute of Technology suppression which equals or exceeds the sound quality produced by a Georgia Institute of Technology digital implementation, with the additional benefits of low power and Georgia Institute of Technology real-time computation. Georgia Institute of Technology Test structures used to collect noise and matching data. Georgia Institute of Technology Band-gap operational amplifier Georgia Institute of Technology Neuron chip with epot structure. Version 2. Georgia Institute of Technology Basic transistor structures. 1st revision. Georgia Institute of Technology Analog computational array for performing speech processing algorithm. Georgia Institute of Technology Analog computational array for performing speech processing algorithm. Georgia Institute of Technology This chip contains several types of continuous-time bandpass filters. Georgia Institute of Technology A chip that mimics the funcition of a dendrite in a neuron. Georgia Institute of Technology This is a simple proof of concept chip. Georgia Institute of Technology A chip that is able to modify itself depending on its inputs. Georgia Institute of Technology This chip has simple feedback and the subcircuits all come out to pins. Georgia Institute of Technology An imager chip using floating gates to do onchip transforamtions. Georgia Institute of Technology A current mode copier chip to store images. Georgia Institute of Technology A second order current mode sigma delta A/D converter chip. Georgia Institute of Technology A chip that is able to modify itself depending on its inputs. Georgia Institute of Technology This chip has simple feedback and the subcircuits all come out to pins. Georgia Institute of Technology This chip has dendritic delays as well and is more complex than chip 2. Georgia Institute of Technology Testing of new structures for non-volitale memeory. Georgia Institute of Technology Including many diffrent structures. Georgia Institute of Technology Testbed for non-volitale systems. This includes many pieces Georgia Institute of Technology to test the whole system including programming structures. Georgia Institute of Technology Neuron chip. 1st revision. No epot structure. Georgia Institute of Technology This chip places differential pair blocks in a programming Georgia Institute of Technology matrix. The programming matrix will enable automatic floating gate Georgia Institute of Technology programming. Georgia Institute of Technology Analog Signal Processing blocks characterization structure. Georgia Institute of Technology A programmable analog array using floating gate technology. Georgia Institute of Technology A 128 by 128 matrix transform chip using floating gates. Georgia Institute of Technology A 16 by 16 matrix transform chip using floating gates. Georgia Institute of Technology A 16 by 16 matrix transform chip using moscaps in the floating gates. Georgia Institute of Technology Self-adapting chip with dendritic delays. There's no feedback. Georgia Institute of Technology Cells can learn and modify itself depending on the input pattern. Georgia Institute of Technology Modified T-gate switches. Wells come out to pins. Proof of concept for new circuit. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Investigate the phase noise of 1 GHz VCO due to different sizes of the MOSFETs. Georgia Institute of Technology Various W/L transistors for providing a noise curve Georgia Institute of Technology Large L transistors carefully laid out for maximum matching Georgia Institute of Technology Photodiode imager with centroid computation and frame differencing. Georgia Institute of Technology Programmable Sigma-Delta A2D using floating gates. Georgia Institute of Technology A noise suppression algorithm implemented as an analog system. Uses bandpass filters and noise and signal estimates to compute a gain per band-limited signal. Georgia Institute of Technology A test chip for the individual elements of a noise suppression system. Georgia Institute of Technology Includes a peak detector, minimum detector, a translinear division circuit, and a gain function/multiplier circuit. Georgia Institute of Technology Series of SOS's with different features. Georgia Institute of Technology This chip will focus on developing an array of second-order continuous-time banpass filters. Georgia Institute of Technology Each element in the array will be programmed with floating gates. Georgia Institute of Technology The overall system will break an input signal into is frequency components. Georgia Institute of Technology This chip contains signal-classification system centered around an array that stores Georgia Institute of Technology signals into one of several quantized vectors by their frequency spectrum. Georgia Institute of Technology test structure for a dense current mode sigma delta array Georgia Institute of Technology an array digital to analog converter using floating gates, also some current mirrors Georgia Institute of Technology an array digital to analog converter using floating gates with a swicth in the input Georgia Institute of Technology This chip has short channel lenght pfet transistors. These Georgia Institute of Technology pfet devices are required for proper operation of the chip. Georgia Institute of Technology This design contains pfet devices with length's smaller than Georgia Institute of Technology the mininum feature length. These short channel devices are Georgia Institute of Technology required for proper operation of the chip. Georgia Institute of Technology Testing of parallel reading of currents on chip. Georgia Institute of Technology This is the 3rd revision of the Neuron chip. Georgia Institute of Technology This contains a floating-gate array. Georgia Institute of Technology There are also several bandpass filters with different ratios of capacitors. Georgia Institute of Technology This is the second version for arrays of bandpass filters. Georgia Institute of Technology There will be two different arrays of thirty-two bandpass second-order Georgia Institute of Technology filters. Each element in both of the arrays will be biased with floating Georgia Institute of Technology gates. Georgia Institute of Technology This chip contains an array of 16 bits D/A converters, and some programing logic. Georgia Institute of Technology A RF chip utilizing a distributed transistor and distributed inductor. Floating-gate elements are used to implement the systems, along with short-channel length transistors. Georgia Institute of Technology This is a 128x128 imager which can be used for performing block transforms on images. Georgia Institute of Technology This is a 48x48 imager to be used for block transforms of images. Floating gates are used to store the different matrix coefficients. Georgia Institute of Technology This is a 16x16 test imager using floating gates. It would be used for motion/ stereo applications. Georgia Institute of Technology The design is NMOS-PMOS power MOSFETs pairs with sensing Georgia Institute of Technology element. The sensing element ratio is 1/100 and is Georgia Institute of Technology located in several points of the die. Georgia Institute of Technology Other test structures are also included. Georgia Institute of Technology NMOS-PMOS Power MOSFETs pair with current-sensing element Georgia Institute of Technology The current sensing ratio in this design is 1/100 and Georgia Institute of Technology it uses the average of 16 sense elements to measure the Georgia Institute of Technology current. The power MOSFETs pair are the essential part Georgia Institute of Technology in DC-DC converter circuits Georgia Institute of Technology NMOS-NMOS and NMOS-PMOS Power MOSFET pairs with sensing Georgia Institute of Technology elements Georgia Institute of Technology The current sensing ratio is 1/1000 in these designs Georgia Institute of Technology and it only includes one current sensing elements. Other Georgia Institute of Technology test structures are also included. Georgia Institute of Technology Design of a high-bandwidth high-capacitive drive op-amp for use in signal processing/filtering Georgia Institute of Technology design comparators Georgia Institute of Technology design a comparator Georgia Institute of Technology design a comparator Georgia Institute of Technology explore the noise property of the MOSFETs Georgia Institute of Technology Structures for high frequency characterization of chip-package interconnects. Georgia Institute of Technology LNA for GSM applications Georgia Institute of Technology LNA for GSM applications Georgia Institute of Technology dc property of the MOSFETs Georgia Institute of Technology dc property of the MOSFETs Georgia Institute of Technology dc testing of the MOSFETs Georgia Institute of Technology on chip inductors Georgia Institute of Technology on chip inductors Georgia Institute of Technology single reduced Hodgkin-Huxley model of a neuron (uses only nap, na, k, and leak conductances) Georgia Institute of Technology nap conductance uses fast activation - next version needs to remove this block Georgia Institute of Technology a continuation of the ver1 design where the ca block has been replaced by another na block (nap conductance) Georgia Institute of Technology test structures using floating gates : multipliers, squaring, summation circuits Georgia Institute of Technology another version of the Hodgkin-Huxley silicon neuron model - Georgia Institute of Technology this version includes a variable slope with the nap conductance Georgia Institute of Technology 12 bit Flash ADC using Floating gate circuits Georgia Institute of Technology Test circuits for (1) high voltage amplifier, (2) translinear divider, (3) autozeroing voltage-to-current peak detector. Georgia Institute of Technology Chip with high voltage epot diff amp, SPI, synapses and dendritic block. Georgia Institute of Technology a continuation of the Hodgkin-Huxley model... Georgia Institute of Technology this version includes three synapses in order to connect other chips Griffith University A small error correcting RAM chip Griffith University Brent Joyce's Pixel Array Griffith University Opi's Pixel Array Griffith University ADC for CMOS Image Sensor designed by Magnus, Satwan & Alok Griffith University CMOS Image Sensor, designed by Group Griffith University Malcolm's Pixel Array Griffith University ALU design used in Design Flow exercise. Griffith University The digital PLL project is done by two postgraduate students, it is a circuit that causes a particular system to track with another one. More precisely, a PLL is a circuit synchronizing an output signal(generated by an oscillator) with a Griffith University reference or input signal in frequency as well as phase. In the locked state, the phase error between the oscillator's output signal and reference signal is zero or very small. When phase error builds up, a control mechanism acts on the Griffith University oscillator to reduce the error to minimum. In this way, the phase of the output signal is actually locked to the phase of the reference signal. PLL can be regard as a feedback control system. We can analyze PLL by using the method that we Griffith University use to analyze control systems. The chip designed by us is just used for testing. No commercial purpose is expected. Griffith University The Associate Memory project was completed by two post graduate students George and Paul. The data is written into the memory cells which is indicated by the address. Address is generated by the decoder, when it reads, the data comes out Griffith University via tri-state buffer if the tag matches. Griffith University The PLL project is completed by two post graduate students Sijinc and Carlos. The PLL contains, a loop filter and a voltage-controlled oscillator (VCO). The components are connected in the forward path of the loop, while the connection Griffith University between the VCO output and one input of the phase comparator is the feedback path of the system. The frequency range of the PLL is from 20 MHz to 80 MHz. The IC has six terminals: Vdd, Gnd, Input, Output, Filter input and Filter output. Griffith University This project was accomplished by a postgraduate student Aaron. It consists of Griffith University Analog multiplexer Griffith University Temperature compensatated oscillator Harvard University Implementation of an electronic version of the game Othello. Takes inputs for user moves from external buttons and switches and produces outputs to describe the current state of the game for both an LCD display and an LED array Harvard University configuration. Harvard University 16-bit ALU performs ADD, SUBTRACT, AND, ORm XOR, NOT, and 16-by-16 two's-complement signed MULTIPLY. Standard process is four steps: load first input, load second input, calculate, and write output. Calculate is one cycle for all but the Harvard University MULTIPLY, which has a 16-cycle calculation step. MULTIPLY also requires an extra cycle at the end to read the second 16 bits of the output. Harvard University Implementation of a pulse-width encoder/transmitter and decoder/receiver in a MOSIS TinyChip padframe. Harvard University Implementation os an office or household lighting and applicance control unit for energy savings and for safety purposes in a 1.5um MOSIS TinyChip SCMOS lambda=0.8um. Harvey Mudd College multiple student projects: adders, FSMs Harvey Mudd College An asynchronous FIFO chip designed by eight freshmen. Harvey Mudd College Array multiplier from VLSI class ported to AMI 0.5m process with new pads Harvey Mudd College freshman bit error rate tester chip Harvey Mudd College Class project Harvey Mudd College Hangman game Harvey Mudd College includes ROM Harvey Mudd College Class project Harvey Mudd College FIR filter Harvey Mudd College Class project Harvey Mudd College Booth-encoded multiplier Illinois Institute of Technology Modified Newton Raphson Divison, Array Multiplier and ALU Illinois Institute of Technology PowerALU Project, ADD/SUB/DIV ALU class project ECE 429 Illinois Institute of Technology 8 bit ALU class project ECE429, Add, Sub, Newton Raphson Divide, Reciprocal Illinois Institute of Technology ECE429 Term project: newton raphson divison and ALU functions. Iowa State University The aim of this project is to design a Bandpass Sigma Delta modulator for Iowa State University use in the baseband block of a Wideband Code Division Multiple Access (WCDMA) Iowa State University down conversion receiver. Iowa State University This project is about characterization of several types of rf transformers including center tapped and toroidal solenoids. S parameters will be extracted for the 3 port and 4 port transformers and 2 port inductors. It also has several PMOS Iowa State University and NMOS rf devices. Iowa State University This project explores the impacts of two passive RF components: an inter-stage inductor and a gate parallel capacitor, on the performance of an inductor-load cascoded common source low noise amplifier with inductive degeneration with Iowa State University various configurations and sizes through design, simulation, fabrication, testing, and characterization. Iowa State University LNA 5 G, 802.lla Johns Hopkins University operational transconductance amplifiers Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University operational transconductance amplifiers Johns Hopkins University support vector test machine chip, computational rows Johns Hopkins University adaptive filter chip Johns Hopkins University operational transconductance amplifiers Johns Hopkins University 40x40 pixel beam width metric and centroid imager Johns Hopkins University operational transconductance amplifiers Johns Hopkins University floating-gate dosimeter study Johns Hopkins University Floating gate kernels Johns Hopkins University design with everything Johns Hopkins University support vector small version, no ADC Johns Hopkins University delta-sigma plus svm, class project 2x2 tiny Johns Hopkins University delta sigma with feedback Johns Hopkins University Stereo circuit test Johns Hopkins University Address-Event Retina Chip Johns Hopkins University Isolation amplifier and Tx modules Johns Hopkins University ratio spectrum chip Johns Hopkins University Chip contains photodetector array and motion cells. Image and Optical flow field is scanned out. Johns Hopkins University potentiostat plus delta-sigma A/D Johns Hopkins University potentiostat plus delta-sigma A/D Johns Hopkins University Transistor matching test array Johns Hopkins University Transistor matching test array Johns Hopkins University A dense array of BJT pixels. Johns Hopkins University Polymer Imager and Tx modules Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University potentiostat plus telemetry Johns Hopkins University potentiostat with delta-sigma A/D Johns Hopkins University Bit-Matrix transpose DRAM Johns Hopkins University Current reference and other test structures Johns Hopkins University Support Vector Machine with forward decoding Johns Hopkins University support vector machine chip, class project 2x2 tiny Johns Hopkins University Capacitive sensor circuit for capacitive sensors. Johns Hopkins University digital multiplier Johns Hopkins University student project: car alarm controller Johns Hopkins University Digital portion of Direct Digital Synthesizer Johns Hopkins University Detector Array for controlling a Deformable Mirror Johns Hopkins University Multi-channel potentiostat with revised clocking Johns Hopkins University Real-time laser beam width metric chip for adaptive optics Johns Hopkins University Acoustic signal processing system with wakeup detector and sound localization circuits Johns Hopkins University Pressure sensor transmitter Johns Hopkins University Alternate pressure sensor Johns Hopkins University Regulator,oscillator,ota,reference Lafayette College WimpNet (simplified Ethernet) receiver. Lafayette College A network transmitter interface for a simple protocol called "WimpNet" which uses collision detection. Lafayette College Network transmitter interface for a simple protocol called WimpNet. Lafayette College Receiver interface for simple network protocol "WimpNet". Lafayette College Transmitter interface circuit for "WimpNet" - simple ethernet-like network protocol. Lafayette College Half-bridge to connect together two "WimpNet" (simplified ethernet) networks together - forwards packets from one net to another. Lafayette College 4-bit successive approximation A/D converter based on voltage-scaling DAC Lafayette College 4-bit Successive-Approximation A/D Converter Lafayette College 4-bit successive approximation A/D Converter Lafayette College 4-bit successive approximation A/D converter Lafayette College 4-bit succ. approximation A/D converter Lafayette College 4-bit successive approximation A/D converter Louisiana State University CMOS VLSI IMPLEMENTATION OF 4-BIT MAGNITUDE Louisiana State University COMPARATORS (2-DESIGNS) Louisiana State University CMOS IMPLEMENTATION OF 4-BIT COUNTERS: Louisiana State University RIPPLE COUNTER, BCD COUNTER, BINARY COUNTER Louisiana State University CMOS VLSI IMPLEMENTATION OF 4-BIT Louisiana State University BIDIRECTIONAL SHIFT-REGISTERS Louisiana State University VLSI IMPLEMENTATION OF A TERNARY-TO-BINARY Louisiana State University LOGIC CONVERSION IN FLOATING GATE MOSFET CMOS Louisiana State University CIRCUIT DESIGN Louisiana State University VLSI IMPLEMENTATION OF A 10-BIT DAC IN CHARGE Louisiana State University SCALING ARCHITECTURE. THE DESIGN INCLUDES TEST Louisiana State University CIRCUITS. Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT ALU IN Louisiana State University FLOATING GATE MOSFETS. THE DESIGN INCLUDES Louisiana State University TEST DEVICES. Louisiana State University VLSI IMPLEMENTATION OF TERNARY TO BINARY LOGIC Louisiana State University DIGITAL CIRCUITS. THE DESIGN ALSO INCLUDES TEST Louisiana State University DEVICES. Louisiana State University VLSI IMPLEMENTATION OF THREE DIFFERENT TYPES OF Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT ALU. THE DESIGN Louisiana State University INCLUDES 4_LOGIC AND 4-ARITHMETIC OPERATIONS. Louisiana State University VLSI IMPLEMENTATION OF A BCD-TO-SEVEN Louisiana State University SEGMENT CONVERTER DESIGN Louisiana State University VLSI IMPLEMENTATION OF TWO 4-BIT COUNTERS- Louisiana State University SYNCHRONOUS COUNTER AND COUNTER WITH PARALLEL Louisiana State University LOADS Louisiana State University VLSI IMPLEMENTATION OF TWO 4-BIT COUNTERS: Louisiana State University BCD RIPPLE COUNTER AND A BINARY COUNTER Louisiana State University VLSI IMPLEMENTATION OF THREE TYPES OF 4-BIT Louisiana State University SHIFT REGISTERS: SERIAL-TO-PARALLE, PARALLEL-TO Louisiana State University -SERIAL AND BIDIRECTIONAL TYPES Louisiana State University VLSI IMPLEMENTATION OF A 4-BIT BINARY COUNTER Louisiana State University WITH PARALLEL LOAD AND A BCD RIPPLE COUNTER Louisiana State University VLSI IMPLEMENTATION OF AN AMPLIFIER IN Louisiana State University CMOS TECHNOLOGY. THE DESIGN ALSO INCLUDES Louisiana State University A SIMPLE TEST INVERTER. Michigan State University This integrated circuit contains a 3-bit counter, a 2-bit ripple-carry adder, a 2-bit pipeline, three inverters of different b values, two ring-oscillators (one standard, one custom) three NMOS transistors, two NOR gates, two NAND gates, Michigan State University two resistors of different sizes, an XOR gate, an XNOR gate, a 4-input OR, a 4-input multiplexer, a tristate buffer, a 4-input AND, a Schmitt Trigger, a transmission gate, an AND/OR invert, a transmission gate XOR, a D flip-flop, a 3-input Michigan State University XOR, a PDN-PUN transmission gate as well as five useful custom logic functions: AB+C, (A+B)C, AB+AC, A’B’C, and ( ).. The contact person is Ellen McKenzie (mckenz33@egr.msu.edu). Michigan State University This integrated circuit contains two 2-Input NAND Gates, two 2-Input NOR Gates, 2 ring oscillators, 2 to 1 Selector as a combinatorial circuit, a 2 to 1 selector as a pipeline circuit, 3 NMOSs, 2 resistors, 3 Inverters of different betas, Michigan State University and a 2-Bit up down counter as a sequential logic circuit. The contact person is Nathan Dotson (dotsonna@pilot.msu.edu) Michigan State University This integrated circuit contains following: 2 ring oscillators, 3 PMOS transistors, 3 CMOS inverters, 2 Resistors, 2 NOR gates, 2 NAND gates, MOD 4 counter, 2 bit adder, and Pipeline circuit. The contact person is Bradley Michigan State University Wynn(wynnbrad@pilot.msu.edu). Michigan State University This circuit contains: 3 NMOS transistors, 3 CMOS inverters, 2 ring oscillators, 2 resistors, 1 four-bit counter, a combinatorial logic circuit, a pipeline logic circuit and the following gates: 2 NOR, 2 NAND, X'Y, Y'X, 4NOR, 4NAND, 3NOR, Michigan State University 3NAND, 3OR, XOR, OR. The contact person is Scott Cogan Michigan State University This circuit contains 3 PMOS transistors, 3 CMOS inverters, 2 ring oscillators, 2 resistors, 2 NOR Gates, 2 NAND gates, a Modulo-4 counter, a combinatorial version two-bit full-adder, a pipeline version two-bit full-adder, and ten unique Michigan State University logic gates. The contact person is Mark Szymczak (szymcza4@msu.edu) Michigan State University This Circuit Contains three NMOS transistors, three CMOS inverters, two NOR gates, two NAND gates, two 75-MHz ring oscillators, 5K Ohm resistor, 50K Ohm resistor, NORC (OR/NOR) gate, two-to-one MUX, three-input NOR gate, three-input NAND Michigan State University gate, 2-Bit Ripple-Carry Adder, 2-Bit Ripple-Carry Adder (Pipeline Implemenatation) and a modul0-4 counter. The Contact Person Is Pedro Barba (barba@msu.edu). Michigan State University This integrated circuit design is a compilation of compilation of devices of various size and complexity. Included are transistors, a wide variety of digital logic gates, ring-oscillators, resistors, (2) 8-bit selectors, and a 3 bit Michigan State University counter. Project Contact: Cory La Count lacountc@msu.edu. Michigan State University Our project contains the following (1) 3 PMOS transistors; (2) 3 CMOS inverters; (3) 2 CMOS NAND gates; (4) 2 CMOS NOR gates; (5) 2 75MHz Ring Oscillators; (6) 1 2-input XOR gate; (7) 1 2-input OR gate; (8) 1 4to1 Multiplexer; (9) Michigan State University 1 Buffer; (10) 1 2-input AND gate; (11) 1 3-input AND gate; (12) 1 2-bit counter; (13) 1 2-bit ripple-carry adder; (14) 1 4-input NAND gate; and (15) 1 4-input NOR gate. Contact Information--Andrew Held email: heldandr@msu.edu. Michigan State University This integrated circuit contains 2 ring oscillators, 2 NANDS, 2 NORS, 3 Inverters, The contact person is Ryan Amman (ammanrya@egr.msu.edu). Michigan State University This integrated circuit contains 2 NAND Gates, 2 NOR Gates, Three PMOS transistors, 2 Ring Oscillators, 3 Inverters, 8 standard cell Logic Gates, and a Microprocessor including eight functions, a Pipeline Adder, a Combinatorial Adder, an Michigan State University Arithmetic Shift Left, an Arithmetic Shift Right, Increment, a Two's Complement, a Compare function, and a Bitwise XNOR. Michigan State University This integrated circuit contains 3 inverters, CMOS NOR, NAND and XOR gates, a pseudo-NMOS XOR gate, two ring oscillators, a MOD5 counter and a One's Counter. The contact person is David Bordoley (bordoley@msu.edu) Michigan State University This project is the final project for ECE410. We built a chip containing a 8 bit comparator, a tail light, a nor gate, a nand gate, a CMOS xnor gate, a Pseudo Xnor gate, three different inverters, and two ring oscillators with varied Michigan State University frequency. Contact person Cecilia Richardson email address:richa186@egr.msu.edu Michigan State University This circuit contains three variable size inverters, 2 ring oscillators, 8-bit comparator, 4-bit shift register, 4 to 1 multiplexor, NAND Gate, NOR Gate and 2 XOR Gates. The contact person is Jacob Alamat (alamatja@egr.msu.edu). Michigan State University This integrated circuit contains 3 inverters of differing P-N Ratios, 2 Ring Oscillators, 1 NAND gate, 1 NOR gate, 1 CMOS XOR Gate, 1 Pseudo-NMOS XOR Gate, a 2-bit Adder/Subtracter, and a taillight controller for a Ford Thunderbird. The Michigan State University contact person is Jeffrey Blank (blankjef@msu.edu). Michigan State University This integrated circuit contains three inverters, a NOR and a NAND gate, a static CMOS technology and a Pseudo-NMOS technology XOR gate, two ring oscillators, a four-bit full adder, and an automotive taillight controller. The contact Michigan State University person is John Lee (leejohn2@egr.msu.edu). Michigan State University This chip contains contains 3 inverters, two ring oscillators, a Xor using Cmos, a Xor using Pseudo-Nmos, a Nand, a Nor, a Mod-8 up and Down Counter and a 4-bit full adder/subtrator. The contact person for design team #7 of spring '01 Michigan State University would be Erich Dams his email is Damseric@msu.edu. Michigan State University This integrated circuit contains an 8 bit A/D converter, three inverters, Pseudo-NMOS and CMOS XOR gates, and two ring oscillators. The contact person is Joshua Schwannecke(schwanne@msu.edu). Michigan State University This integrated circuit contains three custom inverters, two ring oscillators, a 2-input NAND gate, a 2-input NOR gate, a CMOS 2-input XNOR gate, a pseudo-NMOS 2-input (and a bias) XNOR gate, and a 512-bit SRAM memory block. The contact Michigan State University person is Brian McCarthy (mccart85@msu.edu). Michigan State University This integrated circuit contains 3 inverters, a NAND gate, a NOR Gate, a CMOS XNOR gate, a pseudo-NMOS XNOR Gate, two ring oscillators, and 256 bits of SRAM. The contact person is P. D. Fisher (fisher@egr.msu.edu). Michigan State University This integrated circuit contains a four-bit ALU, three inverters, a CMOS NAND gate, a CMOS NOR gate, a CMOS XNOR gate, a pseudo-NMOS XNOR gate, two ring oscillators, and a 4-bit mod12 binary counter. The contact person is Garrett Heraty Michigan State University (heratyga@egr.msu.edu). Michigan State University ECE 410 design team 4 ASIC. This chip contains 2 input NAND, NOR, CMOS XOR and Pseudo NMOS XOR gates. It also has 3 inverters, 2 ring oscillators, a 4-1 digital mux, 3 bit binary counter and a 3-bit adder. Contact Samir Patel Michigan State University . Michigan State University The IC contains several gates, two ring oscillators, a 4-bit up counter, and a 4-bit Conditional Sum Adder. The contact person is Lonnie Halash (halashlo@msu.edu) Michigan State University This integrated circuit contains three inverters, two ring oscillators, two XNOR gates, an 8 to 1 multiplexor, one NAND gate, one NOR gate and a 2-bit binary counter. The contact person is Carl J. Denslow (denslowc@msu.edu). Michigan State University The chip contains three custom inverters, five standard cells (NOR, NAND, CMOS XOR, 4-input OR and Pseudo NMOS XOR), two ring oscillators, a 2-bit adder and a 4-bit counter. Michigan State University This integrated circuit contains an SRAM memory cell, and a test circuit with several small components (inverters, ring oscillator, etc). The contact person is Chris Wozniak (woznia13@msu.edu). Michigan State University This integrated circuit contains full memory block, consisting of a read/write circuit, a controller/decoder, and a SRAM memory core. Contact person is Jim Block at blockja1@msu.edu. Michigan State University This integrated circuit contains three CMOS inverters, one CMOS NOR gate, one CMOS XNOR gate, one pseudo-NMOS XOR gate, two ring oscillators, one four-bit adder/subtractor, one three bit multiplier/divider, and one four-bit binary counter Michigan State University mod-14. The contact person for out group is Dave Warren (warrend5@msu.edu). Michigan State University 8x8 SRAM Memory Core, Row Decoder, Read Write Circuit, and Controller. The contact person is Andrew Deacon (deaconan@msu.edu). Michigan State University This integrated circuit contains three inverters with different P/N ratios, 2 ring oscillators, 2 input NAND gate, 2 input NOR gate, 2 input CMOS XNOR gate, 2 input Pseudo-NMOS XNOR gate, NMOS transistor, 3-Bit decoder, 3-Bit up/down Michigan State University counter. The contact person is zhonghua li (lizhongh@msu.edu). Mississippi State University Interface between DS1620 temperature sensing chip and seven segment LED display. ALso includes other simple functions. Mississippi State University digital padframe testchip Mississippi State University DDFS test structure 2560L 25P 22S Mississippi State University DDFS test structure 2560L 10P 22S Mississippi State University DDFS test structure 2560L 5P 22S Mississippi State University This design is a set of chargepumps and OTAs for proof tests that are needed for an analog IC design class. Mississippi State University initial prototype of 16 bit accumulator with phase detection logic Mississippi State University plus initial prototype of voltage follower based on OTA Mississippi State University revised ROM-less direct digital frequency synthesizer Mississippi State University 2nd generation current mode flash ADC Naval Postgraduate School Programmable GICT switch capacitor filter. Naval Postgraduate School Eight-bit, fast, full carry lookahead adder. New Mexico State University Class AB Op Amp by Carlos Nieva New Mexico State University Fast Op Amp by Mike Holmes New Mexico State University Proto-typing CMOS subcircuits New Mexico State University Proto-typing CMOS subcircuits New Mexico State University Digital Test Chip New Mexico State University This Project will fabricate Analog Adaptive Median Filters. New Mexico State University Inductors/Transformers of various styles, metals, and layout configurations wiil be fabricated. New Mexico State University Digital logic gates to implement Boolean functions New Mexico State University with charge pump and voltage regulator. The functions New Mexico State University are AND, XOR, and a DFF. Different logic styles are New Mexico State University used: static CMOS, CVSL, Pass Transistor Logic, and New Mexico State University Dynamic Logic New Mexico State University This project will fabricate a Multiple Input Linear Weighted Differential Amplifier. New Mexico State University This Project will fabricate a 15th order Rank Order Filter with output selection circuitry. New Mexico State University This project will fabricate a Class AB Op Amp for low voltage applications and a low voltage multiplier. New Mexico State University This project will fabricate test circuitry. New Mexico State University This chip contains two new OTA designs and two configurations for a new low voltage analog mixer. New Mexico State University New OTA Design New Mexico State University This chip contains several new Current Source Designs New Mexico State University This chip contains a new, low voltage, two stage, class AB opamp design. New Mexico State University Nodal analysis Vddq with OTA as circuit under test. New Mexico State University This Chip contains several new Analog Multiplier Designs. New Mexico State University This chip contains several new Analog Multiplier Designs. New Mexico State University This Chip contains several inverter gain stages. New Mexico State University This chip contains a fully differential analog multiplier design. New Mexico State University Rank Order Filter that has new digital circuitry to select specific ranks and allow for better testing control of circuitry. New Mexico State University Testing circuit for floating gate MOSFETS. New Mexico State University Differential Multiple Input Linear Differential Amplifier. New Mexico State University This chip contains 4 Quadrant Multiplier circuits with floating gates. New Mexico State University High Frequency Feed Through Amplifier New Mexico State University High Speed Dynamic Current Sensor New Mexico State University Several configurations of a proposed OTA will be fabricated including a new fully differential version. New Mexico State University Several OTA implementations will be fabricated with Lateral PNP transistors. The chip also contains a single Lateral PNP for characterization. New Mexico State University Rank order filter with four inputs and Current mirrors floating substrate Ohio State University Limter with RSSI Version 1 Ohio State University LPF1 and LPF2 Ohio State University LPF3 and LPF4 Ohio State University HPF1 and HPF2 Ohio State University HPF3 and Attenuator Ohio State University fully differential CCII Ohio State University MOSFET-C Filter Ohio State University MOSFET-C Low Pass Filter Ohio State University Limter with RSSI Version 2 Ohio State University A fully integrated frequency mixer Ohio State University A fully integrated voltage controlled oscillator Ohio State University A bonding diagram has been faxed to you. Ohio State University Please make note of it and let Ohio State University us know wheter you get the fax or not. Ohio State University The Nemesis chip implements the Nemesis Encryption algorithm Ohio State University 5 Bit SAR ADC Ohio State University RF-ID clock and vdd generation Ohio State University low pass filters Ohio State University low pass filters Ohio State University high pass filters Ohio State University High pass filters Ohio State University buffer and attenuator Ohio State University Programmable RSSI Ckt Ohio State University 4-20mA Receiver and 2nd-Order Delta-Sigma Modulator with Ohio State University test opamps and voltage bais circuits Ohio State University The section of the Nautilus chipset is the bare SPI unit Ohio State University that is able to transmit and receive serial bits in a recirculating Ohio State University fashion. Ohio State University This section of the Nautilus chipset provides the Ohio State University decimation and noise shaping of the DSM2's pulse density stream. Ohio State University The part of the Nautilus chipset is the SPI internal Ohio State University latching mechanism necessary for implementing a full scale SPI Ohio State University interface. Ohio State University This is an experimental second order decimation filter Ohio State University that converts a pulse density stream into a 16-bit word. Decimation Ohio State University gain and length are programmable. Ohio State University 4-bit Flash ADC Ohio State University PLL Design 1 Ohio State University PLL Design 2 Ohio State University CMOS EEPROM Design Ohio State University Sonnet Serializer group Ohio State University CAM Design 1 Ohio State University CAM Design 2 Ohio State University Differential Opamp Bias Circuitry Ohio State University Fully Differential Fourth-Order Delta-Sigma Modulator A/D Ohio State University This chip implements the Nemesis encryption algorithm Ohio State University CAM Design 1 Ohio State University CAM Design 2 Ohio State University Flash ADC 4 Bit Ohio State University PLL Design 1 Ohio State University PLL Design 2 Ohio State University complete RSSI circuit Ohio State University SAR ADC 6-bit Ohio State University SONNET Serializer Circuit Ohio State University Wavelet DSP core Ohio State University oscillator for 2.4 GHz Oregon Graduate Institute This is an opamp and a buffer with two inverters. I would like you to fabricate the layout design only on the packaged part, not on the unpackaged parts. Oregon Institute of Technology analog&digital experiments Prairie View A&M University lan hu's comparator chip Prairie View A&M University 3x* DECODER WITH A 5 STAGE CASCADING INVERTER PROJECT DESIGN FOR ELEG 5173 Prairie View A&M University 2 x 4 decoder with enable Princeton University This project is a class project for ELE462 at Princeton University. It is an enhanced DES encryption chip in the sense that both SBOX and PBOX can be programmed. The chip is designed with Cadence tools using NCSU package. Princeton University This is the second chip we are going to fabricate for the spring semester 2001. Purdue University leakage controlled 4k SRAM Queens University of Belfast Two 5.5 GHz amplifiers, standard and linearised Rice University The PRIME chip implements an optimized trial-division method to verify the Rice University primality of an 8-bit unsigned integer input. It uses a ring counter to Rice University exploit the "prime jumping" sequence, significantly reducing the number of Rice University trial divisors that must be tested. It asserts an output signal PRIME Rice University when testing is done if the number has no factors. Rice University ATMCNTRL is the control chip for an ATM machine. The ATM will allow a Rice University manager to add/delete user accounts while the user will have standard ATM Rice University options to choose from. These options include: withdrawal, deposit, and Rice University checking the balance. This chip will interface with the ATM I/O chip. Rice University It is designed to compute the discrete wavelet transform coefficients in a Rice University cascaded FIR style. With simplified algorithm design, we use only one Rice University multiplier and accumulator and some in-chip memory controlled by several Rice University PLAs to get the coefficients {C} and {D} with desired precision.These Rice University coefficients are very useful for applications. Rice University GAMBLER1 implememts a simplified form of the popular casino game Rice University Blackjack. Four inputs from the player control the deal of a hand, a hit, Rice University a stay, and the restart of a game. Player total, computer total, the most Rice University recently dealt "card", and the possible outcomes are displayed as outputs. Rice University The GCF chip calculates the greatest common factor of two 6-bit unsigned Rice University inputs. The output is a 6-bit unsigned integer which represents the Rice University greatest common factor of the two inputs. The chip consists of adders, Rice University programmable logic arrays, and shift registers to perform several divide Rice University and multiply operations. Rice University A (4/8) Hamming encoder/decoder pair. Takes a 4-bit input and Rice University encodes it with error-correcting code, allowing the decoder to check and Rice University correct single-bit errors as well as detect and indicate when double-bit Rice University errors have occured. Provides fault-tolerant data transfer. Rice University This chip performs pipelined detection for WCDMA. First, correlation Rice University matrices and 8-bit soft decisions for each of 5 users are loaded. One-bit Rice University hard decisions representing the past, present and future are used with the Rice University correlation matrices to produce a better hard decision for use by later Rice University pipeline stages. Rice University This chip implements the IDEA encryption algorithm. The chip Rice University takes a 4-bit round number, a 16-bit data block, and a 32-bit key. Rice University The chip executes a series of mathematical operations for the Rice University specified number of rounds. When the last round is Rice University completed, the final 16-bit output of the chip is produced. Rice University Efficient detection and Error correction is of utmost importance Rice University in modern communication. The Viterbi Decoding algorithm is a elegant and Rice University powerful approach in this area. Our Chip implements a rate 1/2 Viterbi Rice University decoder with a traceback depth of 16. The operational clock frequency is Rice University 4.54 Mhz and the maximum input data rate is 94.6 kilobits/second. Rice University ALCOHOL implements a human blood alcohol content calculator. Based on the Rice University type of drink, number of drinks, weight and number of hours drinking, our Rice University chip computes an individual's BAC. Registers store the inputs. Configured in Rice University an accumulator-style, the chip uses an adder (16-bit) and shift register Rice University (32-bit) for computation. Rice University This chip is an instruction scheduler. It operates on a simple 8-long Rice University block of 8-bit instructions, which are found in off-chip memory. The chip Rice University determines which instructions can and should be reordered, using our Rice University dependency and reordering algorithms, and then reorders them in the Rice University off-chip memory. Rice University Our project tries to implement an addtion and subtraction Rice University algorithm in a family of algorithms called Online Arithmetic. It is designed Rice University to do mathematical operations in the unconventional way of MSB to LSB. Rice University This chip processes sixteen by sixteen eight bit grayscale images. It can Rice University perform one of six different functions: inversion, flip horizontally, Rice University flip vertically, smooth by minimum, smooth by maximum, or smooth by Rice University average. Both the source and output images are stored in external memory. Rice University The chip implements the ADPCM voice encoding algorithm. Rice University It encodes 16-bit voice data input stream into 4-bit data Rice University output stream. Necessary control signals are provided to Rice University interface the chip with supporting system to form a Rice University real-time voice encoder. Rice University The Decimal to Fraction Converter takes in a 3-digit decimal number Rice University between 0 to 1. The greatest common factor (GCF) is found for the Rice University input and the number 1000. The numerator (input) and denominator (1000) Rice University are divided by the GCF. The results are outputted as integers Rice University to represent the fraction. Rice University Our project is working with another group to develop a two-chip ATM Rice University controller system. Our chip will be more of a "front end" in the system, Rice University in that it will take input data from a keypad, pass it along to the Rice University second chip, and receive information back that will be sent to a Rice University LCD display unit. Rice University We have done an RSA decryption chip. We use 20 pins for input signals and Rice University 10 pins for output signals. The chip consists Rice University basically of an 8x8 bit multiplier, an 8x8 bit adder, three PLAs, some Rice University static latches and transmission gates. The chip calculates x=m^d mod n Rice University (n=253). Rice University This chip is a basic, general-purpose RISC processor. Rice University It possesses two ALU's, one four-bit and one eight-bit, Rice University which work in parallel, as well as seven general-use Rice University registers and one zero-register. The processor Rice University Mnemosyne is a synchronous digital neural network for pattern Rice University recognition. It has 5 neuron subblocks, a control, and a test Rice University structure. First trained to accept or reject various patterns, it Rice University adjusts its internal values to reflect the desired responses. After Rice University training it can take 64 bit patterns and compare them to the ones it Rice University has been trained for. Rice University Our chip models an scanner which recognizes the integers 0-9 Rice University in seven segment display. The input is represented in an Rice University 8x8 matrix and loaded as a series of zeros and ones. Rice University Upon recognition of a pattern, the chip will output the Rice University number found (in binary) and its corresponding Rice University x,y coordinates. Rice University Our project is to design a chip that carries out LZW compression Rice University on arbitrary-length binary data. The chip will use the basic LZW Rice University algorithm at a binary level. Off-chip SRAM will be used to Rice University implement the 'dictionary'. Rice University The algorithm has two main steps, Rice University A) A search step where the 'dictionary' of known datawords is Rice University searched for matches with the current data. Rice University B) An output step where a codeword is output Rice University Implements a variation on the game of Craps for one Rice University player. The four main sections consist of the main Rice University PLA and a 17 bit RAM cell, the ramdom number Rice University generator, combinational logic for determining the Rice University outcome of the game, and the "bank", which keeps Rice University track of how much money the player has. Rice University FastCPU is a 6-stage fixed point pipeline processor Rice University that executes two instructions in parallel using Rice University data forwarding logic and intermediate result holding Rice University latches. It has three fast, compact functional units, Rice University 8 bit carry look-ahead adder, 8 bit barrel shifter, Rice University 4-bit array multiplier that generates the result Rice University in 8.65ns. This allows a clock speed of Rice University approximately 30MHz. Rice University RAKE correlator in a 40 pin package. Rice University A Rake correlator is a matched filter for a tapped Rice University delay line channel model. They are included in all Rice University wireless devices. Our chip operates at a Rice University maximum frequency of 6.4 chips/sec and outputs Rice University 200Kbits/sec. Rice University This chip does Huffman coding and decoding. The Rice University chip can be either set as an encoder or a decoder. Rice University It encodes or decodes 26 letters of the alphabet Rice University plus 6 symbols; the code words are predefined. This Rice University chip can be used standalone or connected to another Rice University chip of opposite function. Rice University Our chip solves the shortest path problem by implementing Rice University Dijkstra's algorithm. The problem takes in a network of Rice University vertices connected via edges of different weights and Rice University determines the shortest path from a given vertex to any Rice University other vertex as well as the total cost of that path. Rice University Our chip simulates communications on an I2C bus between a Rice University master and slave. The master sends or receives the data and Rice University clock signal through two data lines into the chip. The master's Rice University information is routed to the appropriate slave device, an adder, Rice University with the chip's internal I2C engine. Rice University The chip implements a Cyclic Redundance Check (CRC) utilizing Rice University a table based algorithm. The system operates with any 8-bit generator Rice University polynomial on packet sizes of up to 256 bits. Two chips can be connected Rice University together to perform transmitting and receiving functions. Rice University We have designed a chip that takes in a date (month, day, Rice University year) as an input and outputs the corresponding day of the week with Rice University respect to the modern Gregorian calendar. Rice University The COordinate Rotation DIgital Computer (CORDIC) utilizes an iterative Rice University addition method to solve trigonometric relationships involved in plane Rice University coordinate rotation and conversion from rectangular to polar coordinates. Rice University The algorithm is a sequence of pseudo rotations resulting in a final Rice University rotation through an angle or a final angular argument of zero. Rice University Our chip calculates the determinant of a three by three matrix Rice University whose elements are of length 6 and are two's complement. It utilizes a Rice University variable input size multiplier and adder. The output is a selectable 6-bit Rice University number representing the most significant, middle significant and least Rice University significant bits. Rice University My circuit takes advantage of interesting similarities between analog Rice University semiconductor circuits and neurons to emulate the behavior of the R15 Rice University neuron. This circuit consists of four such neurons in a ring configuration. Rice University This configuration gives rise to emergent properties not observed in the Rice University single neurons; specifically, four distinct firing patterns that imitate Rice University those in a neural pattern generator that controls the gait of a quadruped. Rose-Hulman Institute of Technology This project contains a circuit that models the behavior Rose-Hulman Institute of Technology of sarcomeres. The circuit will produce force-length Rose-Hulman Institute of Technology curves and force-velocity curves according to a set of Rose-Hulman Institute of Technology parameters. Rose-Hulman Institute of Technology This chip is an analog model of a biological sarcomere. It consists of multiple OTA's that interact to simulate Rose-Hulman Institute of Technology attachment and detachment of crossbridges, and movement of charge along a unidirectional delay line to Rose-Hulman Institute of Technology simulate crossbridge movement within a sarcomere due to velocity. There is also a bump circuit that simulates Rose-Hulman Institute of Technology force-length characteristics and a capacitively coupled current conveyor circuit that calculates the velocity Rose-Hulman Institute of Technology according to length changes. Please note: The capacitively coupled current conveyor has two DIBL FETs that Rose-Hulman Institute of Technology are smaller than minimum feature size. These DIBL Fets help to linearize this circuit to produce equal positive Rose-Hulman Institute of Technology and negative derivatives. Rose-Hulman Institute of Technology This chip contains an array of flip-flops with properly distributed power and ground rails. The clock line was Rose-Hulman Institute of Technology layed out in a serpentine configuration to demonstrate the effects of clock skew. The output of the clock was Rose-Hulman Institute of Technology taken off chip to see the RC delay on the clock. Several flip-flop outputs along the array were taken off chip Rose-Hulman Institute of Technology to demonstrate the effects of clock skew on latching the input data. Rose-Hulman Institute of Technology This chip contains an array of flip-flops with properly distributed clock. The power and ground rails were Rose-Hulman Institute of Technology layed out in a serpentine configuration to demonstrate the effects of power/ground bounce. The output of Rose-Hulman Institute of Technology the rails were taken off chip to see the RC delay on the clock. Several flip-flop outputs along the array Rose-Hulman Institute of Technology were taken off chip to demonstrate the effects of latching the input data on the power and ground rails. Rose-Hulman Institute of Technology This chip contains several FETs and current mirrors organized in different configurations. These circuits are Rose-Hulman Institute of Technology intended to show transistor mismatch due to process variation. The current mirror configurations include: Rose-Hulman Institute of Technology (i) scaling the current by sizing the 2nd transistor versus using a repeated cell, (ii) mismatch when creating Rose-Hulman Institute of Technology a pFET current source starting with an nFET current sink, and (iii) creating an array of mirrored outputs using Rose-Hulman Institute of Technology a normal array, using a common centroid layout, and using a common centroid layout with dummy lines. Rose-Hulman Institute of Technology This chip contains several analog and digital circuits on the same substate. The analog circuits are high Rose-Hulman Institute of Technology performance OTAs (using cascoded biases and common centroid inputs). The digital circuits consist of a Rose-Hulman Institute of Technology ring oscillator that can be driven or connected in ring oscillator mode. These circuits are placed near each Rose-Hulman Institute of Technology other on the substrate with and without protective guard rings and separate power and ground rails. The Rose-Hulman Institute of Technology intent is to observe the effects of substrate noise on the analog circuits. Rose-Hulman Institute of Technology This chip is a CMOS push-pull op-amp with capacitor compensation. This chip contains 6 op-amps to Rose-Hulman Institute of Technology test parameter variation across the chip. The op-amps should perform as a unity gain buffer for Rose-Hulman Institute of Technology frequencies up to 500kHz or greater. The input common mode range should be 1 volt peak-to-peak. San Jose State University 4 bit ALU designed in our intro to IC design class at SJSU San Jose State University This is an ADDER that was designed in out into to IC design at SJSU. San Jose State University A 4 bit UP DOWN Counter designed in our intro to IC design class at SJSU. Santa Clara University BIST Enhanced 3-Port IEEE 1394A Southern Illinois University This project contains four different op-amps, as well as two resistors and one npn bjt. This is my first submission to MOSIS, and the first by our school using AMI 1.5 technology. Southern Illinois University Since my design is broken up into several pieces, I'm unsure of the X and Y design size, so I specified the area in the pad. Southern Illinois University This design includes four op-amps and one bjt cascode current mirror. Southern Illinois University This design includes several high frequency op-amps. Stanford University The chip contains analog DLL that is surrounded by a digital DLL. Stanford University The analog DLL has 8 differential stages and locks at pi. The digital Stanford University DLL interpolates between the analog DLL outputs to create 1 of a 128 Stanford University possible clocks. The FSM controller contains a counter that is used to Stanford University select that output of the digital DLL based on a phase compare with an Stanford University external clock. Stanford University RIP (Rapid Initial Phase guess) is a clock recovery circuit that can lock Stanford University to an unknown phase in minimal time. Stanford University Stanford Microcontroller for Robotics Applications--An 8-bit Stanford University microcontroller with three 4-bit A/Ds, two DC motor ports, one servo motor Stanford University port, and one 4-bit digital I/O port. Stanford University CAM-based lookup table with longest prefix matching Stanford University Single Instruction Multiple Data (32b/16b) Floating Point Stanford University Adder Stanford University Differential LC oscillators operating at 2.4GHz. State University New York Buffalo The project implements a pop machine controller, designed in State University New York Buffalo the VLSI class CSE 4/597 in Fall 2000. State University New York Buffalo This project presents Power and Speed Analysis of Sense State University New York Buffalo Amplifier in SRAM, designed in the VLSI class CSE4/597 State University New York Buffalo in Fall 2000. State University New York Buffalo This project implements a 8-bit ALU, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a 5-bit*5-bit Wallace Tree State University New York Buffalo Multiplier, designed in the VLSI class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a Quadrature Decoder, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a Matrix Determinant Simulator, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a 8-bit ALU, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a Floating Point Multiplier, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo This project implements a Digital Celsius to Fahrenheit Converter, designed in the VLSI State University New York Buffalo class CSE4/597 in Fall 2000. State University New York Buffalo Four bit Analog to Digital Converter using CMOS folded Cascode OpAmp in comparators by John Keller, Jeff Weaver and Chris Parkinson. Testing to be done by john Keller -- careful in clocking and pads. State University New York Buffalo The A/D converter uses an array of 7 voltage comparators to convert an analog input voltage varying from +0V to +5V into a 3-bit digital output signal. Each voltage comparator is assigned a reference voltage, to determine if the analog State University New York Buffalo input falls within a particular voltage range. The NOR-gate decoding logic parses the information from the comparators into the 3-bit digital output, b0, b1 and b2. State University New York Buffalo An 8-bit DAC implemented with an R-2R ladder, a CMOS switch State University New York Buffalo network, and a folded cascode operational amplifier in the weighted summer configuration. State University New York Buffalo This project compares three CMOS folded cascode opamps for their matching properties. State University New York Buffalo This project designs a 2x2 Matrix Determinant Calculator which takes four 4-bit unsigned numbers (a, b, c, d) as in State University New York Buffalo puts that are the elements of State University New York Buffalo a 2x2 matrix and calculates the determinant (ad-bc) of the matrix. State University New York Buffalo This project designs a 8-bit ALU which includes adder/subtractor, State University New York Buffalo shifter and AND, OR, XOR logic functions. State University New York Buffalo This project designs and implements a fully functional circuit State University New York Buffalo that handled Fahrenheit to Ceisius temperature conversions based State University New York Buffalo on the standard equation Tc=5/9*(Tf-32). State University New York Buffalo This project is a 4bit high speed calculator which used an adder/ State University New York Buffalo subtractor with a look ahead carry generator to do the adding and the State University New York Buffalo subtracting, and an array multiplier for the multiplication State University New York Buffalo implementation. State University New York Buffalo This project designs a 6-bit Wallace Tree Multiplier. State University New York Buffalo This project designs a 8-bit ALU with logic, shift and arithmetic State University New York Buffalo operations. State University New York Buffalo This project designs and implements the sequential logic design of State University New York Buffalo a traffic light controller. State University New York Buffalo This project designs and implements a 8-bit ALU which includes State University New York Buffalo Add/Subtrsct, shift, and various logic functions, such as XOR, OR, AND. State University New York Buffalo This project designs and implements a 8-bit Wallace Tree Multiplier State University New York Buffalo which contains Wallace Tree accumulators and Carry Lookahead adders. State University New York Buffalo This project implements a design for computation of the frequency State University New York Buffalo domain output of an FIR filter. State University New York Buffalo This project implements a array multiplier which includes CSA part and State University New York Buffalo final adder part. State University New York Buffalo This project implements a 8-bit ALU which includes ADDER/subtractor, State University New York Buffalo XOR, OR, AND logic functions State University New York Buffalo This project implements a 8-bit CSA arry multiplier design. It State University New York Buffalo makes use of standard and and or gates to make up rows of CSA adder State University New York Buffalo blobks. At the last row a carry propogate adder is used to abtain State University New York Buffalo the final product. State University New York Buffalo OpAmp, Diff Amp, and PMOSFET devices by Zhao Tang State University New York Buffalo Project by Z.Wang and others. 1 OpAmp, 1 DiffAmp, 2 Lateral PNPs, 6 PMO transistors. State University New York Buffalo Diff Amp, OpAmp, and 6 PMOS devices by Yili Quan and others State University New York Buffalo Design by Ed Conrad et al: opamp, diff amp, npn, nmos State University New York Buffalo amp project by matt bell et al.: diff amp, opamp, pmos transistors Texas A&M University On chip spectrum analyzer using SC filter Texas A&M University bandpass filter implementation using charge pump device Texas A&M University Interface trap charge pump analog test chip Texas A&M University ADC-Folding Fast circuit Texas A&M University to test the function of sensor and processor Texas A&M University Interface trap charge pump temperature sensor Texas A&M University Four different version of high gain, high GBW OTA's Texas A&M University are designed using NCFF compensaton Texas A&M University Educational Free Run Texas A&M University Analog Turbo Decoder Texas A&M University Texas A&M University Texas A&M University A high frequency novel OTA used in a novel tuning scheme Texas A&M University This is a seventh order equiripple linear phase filter tunable from 10 to 100 MHz Texas A&M University Wide Band Variable Gain Amplifier Texas A&M University Cintinuous time sigma delta modulator building blocks Texas A&M University In this chip, a current mirror based Variable Gain Amplifier is implemented. This VGA is designed to have 36dB gain with more than 100MHz bandwidth. Texas A&M University spectra Texas A&M University On- Chip spectrum analyzer using switched-capacitor techniques to test linear circuits Texas A&M University PLL tuning circuit Texas A&M University This project is a design of a modified Weaver image rejection mixer. Texas A&M University The idea of the project is to detect phase and gain mismatches and Texas A&M University correct for them. This will improve significantly the amout of image Texas A&M University rejection. The input stage is a LNA and followed by the mixer circuit. Texas A&M University Bluetooth Receiver System Texas A&M University Bluetooth Receiver Blocks Texas A&M University variable amplifier for very high frequency application Texas A&M University Ultra Lou Frequency Band Pas Texas A&M University This is a direct digital frequency synthesizer. Clock frequency is 100 MHz. Texas A&M University A variable gain amplifier is implemented using cascaded current mirrors. Texas A&M University The current gain per stage is 6 dB and the bandwidth is 50 MHz. Texas A&M University A new automatic tuning scheme for high frequency filters is Texas A&M University implemented. The chip is composed of a PLL frequency synthesizer, Texas A&M University an OTA-C bandpass filter, and the proposed tuning circuitry. Texas A&M University This is a chip for several NGCC 4-stage amplifiers designed by ELEN 689 Texas A&M University Advanced Analog Circuit Design course students. This chip will be characterized Texas A&M University and be used in future labs for this course for the experimental exercise. Texas A&M University Bandpass sigma delta modulator with NCFF OTA in TSMC 0.35u technology Texas A&M University The project includes a bandpass filter with a Q of 20 Texas A&M University Sigma-delta analog-to-digital conversion using continuous-time Texas A&M University techniques which has the advantage of low-power consumption or Texas A&M University higher speed compared with switched-capacitor ones. Texas A&M University 2GHz Monolithic Sigma-delta Fractional-N Frequency Synthesizer Texas A&M University An analog line driver for video applications utilizing Texas A&M University a class AB error amplifier structure with an adaptive Texas A&M University tuning scheme for output impedance matching using peak Texas A&M University detection. The design achieved 1.2 V peak to peak output Texas A&M University swing with better than -48 dB linearity for frequencies Texas A&M University up to 5 MHz with a tuning range of 65 to 135 ohms and Texas A&M University power consumption of about 34 mW. Texas A&M University An automatic tuning scheme for on-chip BP filter is implemented. The project includes a 2nd OTA-C filter, A PLL-based frequency synthesizer and switch-capacitorcircuits. Texas A&M University This project is to design, layout, and characterize a 4th-order linear phater. This filter features a wide linear signal swing and wide cutoff tunable range. Texas A&M University This is the second version of the ctsigma project. Texas A&M University folding A/D converter (Update) Texas A&M University Voltage Regulator Texas A&M University Implementation of a proposed BP filter tuning scheme. VCO, 2nd order BP filter Texas A&M University and tuning circuitry are included. Texas A&M University This is a 1.8V 2-2 Cascade 4th order single bit Sigma-Delta Modulator with 1MHz signal bandwidth. Also, by modifing the Sigma-Delta structure, the output swing of each integrator is reduced within 0.5 times the reference voltage whlow Texas A&M University voltage operation easy Texas A&M University This chip is used to extract range information of an object. The size of chip Texas A&M University is 3um*3um, using AMIS C5N technolgy. Texas A&M University This chip is used to tested the idea of range extraction using sampling Texas A&M University clock. The chip size is 3um*3um, using AMIS C5N technology. Texas A&M University a lc filter and its tuning circuit Texas A&M University On chip spectrum analyzer for testing analog ICs including algorithmic ADC University of Alabama, Huntsville Project for Jayagopalan, Loo, Maziar, and Steve University of Arizona An Auto-Balanced A/D Noise Source University of Arkansas LOWPASS FILTER CHIP University of Arkansas CMOS Gilbert Cell Mixer University of Bridgeport Main Controller module for a robotic vehicle. University of California, Irvine analog to digital convertor University of California, Irvine An electrical/optical sensor with analog signal storage. University of California, Santa Barbara This project deals with the creation of a keyboard University of California, Santa Barbara emulator. Its basic functionality is to receive the signals University of California, Santa Barbara of a key(s) pressed on a keyboard and rearrange them so that University of California, Santa Barbara they can be displayed on the monitor. This circuit handles University of California, Santa Barbara many cases related to a normal keyboard usage, such as multiple University of California, Santa Barbara keys being pressed at the same time. It generates useful output University of California, Santa Barbara signals which refer to a key being pressed, released and its University of California, Santa Barbara unique code, so that it can be displayed properly. University of California, Santa Barbara The project attempts to calculate the position, University of California, Santa Barbara velocity and acceleration of a DC motor.The output University of California, Santa Barbara is sent to LEDs for display. The chip takes input University of California, Santa Barbara as quadrature encoded signals which are decoded to University of California, Santa Barbara give position. It is then differentiated to give University of California, Santa Barbara velocity. This,in turn is differentiated to give University of California, Santa Barbara acceleration. University of California, Santa Barbara The timer project is a design of a circuit University of California, Santa Barbara with the functions of clock, alarm, stopwatch University of California, Santa Barbara and countdown. A crystal oscillator supplies University of California, Santa Barbara the fundamental frequency, driving a number University of California, Santa Barbara of counters. The output signals are translated University of California, Santa Barbara for LED display. University of California, Santa Barbara This project is a PVA computer. It is University of California, Santa Barbara supposed to keep track of position, velocity, and acceleration University of California, Santa Barbara of a small DC motor, when the motor motion is encoded in University of California, Santa Barbara the form of a pair of square wave signals in quadrature. University of California, Santa Barbara The output of the calculations is selectable (P,V or A), University of California, Santa Barbara and will be sent out in BCD; the BCD however, is encoded University of California, Santa Barbara so that it may control a 7-segment LED display. There are University of California, Santa Barbara four BCD digits, and the four will be multiplexed on the 7 University of California, Santa Barbara lines. Remaining pins are used for test purposes. University of California, Santa Barbara Netproc is a network processor that watches University of California, Santa Barbara the physical layer of ethernet for particular packets. The University of California, Santa Barbara processor can look for 3 different types of packets on a University of California, Santa Barbara 10baseT network. The program is stored externally in a fifo. University of California, Santa Barbara This project is a change maker for a vending University of California, Santa Barbara machine. It uses a PLA for the finite state machine. This University of California, Santa Barbara device can handle 8 different programmable prices and will University of California, Santa Barbara be responsible for making the decision if the user inputted University of California, Santa Barbara enough change for their desired item. It makes change if University of California, Santa Barbara the user inputted more than enough money. University of California, Santa Barbara This chip represents a controller of a vending machine. It contains University of California, Santa Barbara the following inputs :(4) value of the coin (4) product selection University of California, Santa Barbara (1) price set (1) reset ; outputs: (3) coin dispense (1) product University of California, Santa Barbara dispense (11) LED display. The rest are test pins that also may University of California, Santa Barbara interconnect different parts of the circuit. The price of the University of California, Santa Barbara product can be changed by correctly choosing product selection and University of California, Santa Barbara pushing "set price". The coin values are synchronously received University of California, Santa Barbara from the outside; price is subtracted from the value, the "product University of California, Santa Barbara dispense" signal is given, and the corresponding "coin dispense" University of California, Santa Barbara signals follow. University of California, Santa Barbara This design takes a quadrature encoded signal from University of California, Santa Barbara a physical motor then calculates the position, velocity University of California, Santa Barbara and acceleration computed relative to an external clock. University of California, Santa Barbara Two 16 bit position registers compose the high and low University of California, Santa Barbara words of a 32 bit position register. Two more 16 bit University of California, Santa Barbara registers hold the velocity and acceleration. The University of California, Santa Barbara rate at which the velocity and acceleration are updated University of California, Santa Barbara can be controlled with a variable clock divider. University of California, Santa Barbara This chip is a controller for a vending machine. The University of California, Santa Barbara machine has programmable prices and accepts coins, University of California, Santa Barbara dispenses products, and makes correct change. University of California, Santa Barbara This chip is a controller for a scrolling message display. The University of California, Santa Barbara display can scroll from left to right, up/down, and down/up. A University of California, Santa Barbara maximum of seven characters can be input and displayed at a University of California, Santa Barbara time. The output is displayed on a 32x7 LED matrix display. University of California, Santa Barbara This project is an array of 48x16 bits of SRAM. University of California, Santa Barbara The sram cell consists of the standard 6 transistor cell with University of California, Santa Barbara an additional transmission gate for reading out. This array University of California, Santa Barbara will be tested for speed with the use of an on-chip ring University of California, Santa Barbara oscillator and 9-bit counter to automatically generate the University of California, Santa Barbara addressing bits. The automatic addressing will allow data to be University of California, Santa Barbara written up to 250Mhz. The data word is 4 bits long and therefore University of California, Santa Barbara each row contains 4 words. University of California, Santa Barbara This project is a test of several different University of California, Santa Barbara styles and sizes of SCMOS programmable logic University of California, Santa Barbara arrays. We are submitting this to verify that University of California, Santa Barbara recent changes made to the mpla tile set are University of California, Santa Barbara successful. University of Canterbury Multi-project chip: 12 by 4-bit ALU student designs for course ENEL435 (IC Engineering II) University of Cincinnati Stack University of Cincinnati Stack University of Cincinnati Sorter University of Cincinnati Movemachine University of Cincinnati Sorter University of Cincinnati Multiplier University of Cincinnati Sorter University of Cincinnati SIP University of Cincinnati Sorter University of Cincinnati Sorter University of Cincinnati Multiplier University of Cincinnati Multiplier University of Cincinnati Stack University of Cincinnati Stack University of Cincinnati Multiplier University of Cincinnati Tiny Chip - 80-bit binary tree comparator (Huang Requi, Wang Honghao) University of Cincinnati Tiny chip - Linear array sorter (M. Ding, W. Yang, J. Liu) University of Cincinnati Tiny Chip - Binary Tree Comparator (J. University of Cincinnati Rajagopalan, S. Subramanian) University of Cincinnati Tiny Chip - Linear Array Sorter (S. University of Cincinnati Gowrisankar, V. Chamarty) University of Cincinnati Tiny Chip - Linear Array Sorter (S. University of Cincinnati Medepalli, S. Durbha) University of Cincinnati Tiny Chip - North-East Route Checker (S. University of Cincinnati Subramanian, S. Balasubramanian) University of Cincinnati Tiny Chip - Palindrome Checker (X. Zhu, University of Cincinnati H. Li) University of Cincinnati Tiny Chip - Palindrome Checker (S. Kher, University of Cincinnati H. Venkataramani) University of Cincinnati Tiny Chip - Palindrome Checker (A. University of Cincinnati Gurumurthy, V. Narayanan) University of Cincinnati Tiny Chip - Palindrome Checker (V. University of Cincinnati Vijay, P. Cherukuri) University of Cincinnati Tiny Chip - Palindrome Checker (M. University of Cincinnati Shade, W. Welch) University of Cincinnati Tiny Chip - Russian Peasant Multiplier University of Cincinnati (J. Xin, H. Yang) University of Cincinnati Tiny Chip - Russian Peasant Multiplier University of Cincinnati (A. Mishray, D. DSouza) University of Cincinnati Tiny Chip - Russian Peasant Multiplier University of Cincinnati (K. Chandra, S. Premkumar) University of Cincinnati Tiny Chip (0.5 um) - Instruction Stream University of Cincinnati Processor (C. Eaton, A. Munch) University of Cincinnati smart-pixel capable of compensating attenuation , and subsequent comparison University of Cincinnati test chip of 8 by 8 readhead device for page-oriented optical memory University of Connecticut General Purpose Op Amp University of Connecticut Pipelined A/D Converter University of Florida Thresholded imager with all pins University of Florida Thresholded imager with an extra pixel University of Florida 10th order ratio spectrum University of Florida 10th order ratio spectrum University of Florida 32 n-well to p-substrate photodiode pixels for testing University of Florida 32 n+ diffusion to p-sub photodiode pixels University of Florida 32 p+ diff to n-well photodiode pixels University of Florida Haar transform implementation for image compression University of Florida Chemistry chip University of Florida Mixed Signal Flash Converter University of Florida One pixel testing University of Florida 16x16 array testing University of Florida 32 by 32 wide-dynamic-range CMOS imager using AAC readout scheme University of Florida Log Domain Filter project University of Florida A 4*4 modified Haar transform array University of Florida A CMOS imager sensor for high dynamic range application. University of Florida "Full KII" set in Freeman's model to implement a simple subset of olfactory system University of Florida "Reduced KII" in Freeman's model to implement a simple subset of olfactory system University of Florida 8 BIT ALU PROJECT University of Florida This chip is used to test the feasibility of MUX University of Florida 2 potentiostats with on-chip electrodes. University of Florida 2 POTENTIOSTATS WITH ON-CHIP ELECTRODES University of Florida Linear Dynamics Chip University of Florida DPS, comparator and AAC readout scheme test for UFC0210 ultra-wide dynamic range CMOS imager University of Florida cmos imager University of Florida A revised 32 by 32 pixels CMOS imager for ultra-wide dynamic range imaging University of Florida Modified reduced KII set University of Florida Modified full KII set University of Florida Potentiostat to measure very low currents University of Florida Delta Sigma A/D Converter University of Florida Neural Oscillator University of Florida A 32 by 32 pixels CMOS imager for ultra-wide dynamic range imaging using two degrees of freedom time domain sampling technology University of Florida A low power version of 32 by 32 CMOS imager University of Florida a 32x32 TBAR imager with O_E signal University of Florida a TBAR imager with 2 phase clock University of Florida reduced KII set with buffered outputs University of Florida a 2_phase imager University of Florida 2 electrode potentiostat University of Florida 2 electrode potentiostats University of Florida a revised cmos imager University of Florida This chip is used to simulate the electronic neuron. University of Florida This chip is for computing Ratio Spectrum of Speech signal and testing the properties of floating gate transistor. University of Florida This chip is to implement the system identification experiment based the gamma adaptive filter. University of Florida Hardware implementation of reduced KII in olfactory system. University of Florida the goal of the ic is the implementation of a nonlinear University of Florida function. University of Florida Potentiostat University of Florida All pass filter - curr mode University of Florida floating gate University of Louisville In this project, An 8-bit Carry-Lookahead adder circuit is designed. University of Louisville This design reduces the delays introduced to the carry bits using the ripple carry design. University of Louisville In this design the propagation delay for the carry bits is reduced to three gates, University of Louisville compared to several gates in the ripple adder design. University of Louisville 8-BIT 2'S COMPLEMENT RIPPLE CARRY ADDER/SUBTRACTOR WITH OVERFLOW DETECTION University of Louisville This circuit allows a signed, 8-bit binary number (B0-B7) to be added to or University of Louisville subtracted from a second, signed, 8-bit binary number (A0-A7). University of Louisville The circuit is capable of adding or subtracting 8-bit signed numbers where the result University of Louisville is between -128 and +127. Positive numbers have a 0 in the msb position. Negative University of Louisville numbers have a 1 in the msb position. Negative numbers are in 2's complement form. University of Louisville Subtraction is performed by complementing the B bits (input C = 1), adding 1 University of Louisville to the complemented result, and adding this result to the A bits. Overflow detection University of Louisville is provided to detect when the result is ouside of the allowable range. Inputs University of Louisville and outputs are transferred in and out of the circuit using two clock inputs and a write input. University of Louisville This circuit uses the basic NAND,NOR,INVERTER and EX-OR gates for performing the addition and subraction.Two 8-bit vectors a and b are given as inputs to the circuit.The circuit consists of two 4-bit adders and these are connected to form University of Louisville an 8-bit adder.Eight XOR gates are used to facilitate the subraction operation. University of Louisville These XOR gates are connected to vector inputs b .The control bit CC is used to select the University of Louisville operation to be performed.If the control bit CC is 1,then the circuit performs substraction and vector input b is substracted from vector input a.If the control bit CC is 0 then both the input vectors a and b are added and if any carry University of Louisville results,is passed to carry out bit University of Louisville Our chip converts a 4 or 8 bit parallel signal to a serial signal. University of Louisville The input is represented by 8 simultaneous parallel inputs of zeros and ones. University of Louisville Upon recognition of a pattern, the chip will output the corresponding serial output of zeros and ones. University of Louisville The circuit is basically a sequential logic recognition University of Louisville circuit. University of Louisville It comprises of 8 flip-flops connected together and 8 XOR gates connected University of Louisville sequentially. The AND gate is always enabled at ono of its input. The clock University of Louisville pulse given is positive edged pulse. The 3-input And gate is tied up to 2 University of Louisville AND gates and 9 inverters. 8 Flip-flops tied up to 8 XOR gates with inputs University of Louisville in a range from P7-P0. Mod counter is tied up to the circuit to give the University of Louisville required output. University of Louisville The project involved designing a chip used for phase modulation or University of Louisville encryption. The phase modulation requires a digital signal. The chip will University of Louisville provide apparently random digital serial output for the modulation circuit. University of Louisville The digital output is a continuous string of 4-bit long words. The 2-bit University of Louisville KEY input and the clock are extracted from the original radio signal, which University of Louisville synchronizes the chip with the signal. The key inputs are used to select University of Louisville reset state output or one of three 4-bit words to be shifted out serialy to University of Louisville the output. After the last of 4 bits in one string is shifted out, the key University of Louisville is reevaluated to select the next string. University of Louisville Aplication: One will require the same modulation/demodulation system on both University of Louisville ends of the radio transmission. Both transmitting and receiving station University of Louisville will need the chip designed in this project. At the receiving end one will University of Louisville provide the key to do the modulation and also multiply the signal with the University of Louisville key and the clock, to where they can be extracted at the receiving end. University of Louisville This project is designed to hold a 337 bit image and refresh it on a 7x48 University of Louisville led display. Data is loaded into the chip one column at a time University of Louisville controlled by a PC. University of Louisville BCD up/down counter basically deals with counting University of Louisville the number of pulses given as input. The BCD counter University of Louisville with which we are dealing is a 16bit bcd up/down counter. University of Louisville It can count the pulses both in forward and reverse University of Louisville direction ie up counting and down counting. University of Louisville In up counting the input to the AND gate is given University of Louisville from Q of the T-Flipflop and in down counting the University of Louisville input to the AND gate is given from the Q1. University of Louisville The BCD counter which we are dealing with is Asynchronous University of Louisville counter.It can count up to 65535 number of pulses. University of Louisville We can increase the number of count by increasing University of Louisville the number of flipflops and And gates.So a counter University of Louisville can be used to count pulses of any number. University of Maine PID Controller Project University of Maine G. Chen, Z. Lin, and J. Zhou University of Maine December 2000 University of Maine Sigma Delta Modulator University of Maine A. Blais and J. Ferris University of Maine December 2000 University of Maine AutoRanging Circuit Project University of Maine B. French, J. Cousins, and U. Karaoz University of Maine December 2000 University of Maine PLL Project University of Maine B. Atkinson, R. Bethel, and C. Silvestri University of Maine December 2000 University of Maine For details, see web site: University of Maine http://www.eece.maine.edu/vlsi/SigmaDelta University of Maine For details, see web site: University of Maine http://www.eece.maine.edu/vlsi/Pipeline University of Maine See Web Page: University of Maine http://www.eece.maine.edu/vlsi/Digital_PLL University of Maine For description, see: University of Maine http://www.eece.maine.edu/vlsi/Class_D/ University of Maryland Bernoulli Cell Based Circuit University of Maryland NeuronMOS basic circuits University of Maryland Neuron MOS test chip University of Maryland (15,4) (7,3) counter and 4-bit A/D University of Maryland 8 and 16 bit CMOS and neuronMOS parity checkers. University of Maryland neuron MOS 15-4 counters University of Maryland A Current Mode VLSI Degree-Two Chaos Generator University of Maryland 2-limit oscillator University of Maryland VLSI for eleminating clock feed through University of Maryland sinewave show University of Maryland Address-Event Transceiver Chip with New Synapse Circuits University of Maryland Chemfet Sensor University of Maryland 4 neuMOS gate circuit, b type University of Maryland neuMOS gate circuit, CMOS circuit University of Maryland Adders, counters, analog inverters and linear amplifiers. University of Maryland neuMOS gate circuits, a type University of Maryland 4 gate circuit type b University of Maryland 4 gate circuit type a University of Maryland neumos 0.5u circuits University of Maryland neumos 0.5u circuits University of Maryland A current mode degree-two chaos generator University of Maryland 32-bit ID chip using XOR gates for encryption University of Maryland 2-limit onchip oscillator University of Maryland Test Structures for Low Power Analog Course University of Maryland CURRENT-MODE COCHLEA MODEL University of Maryland excitatory and inhibitory neuron circuits for ILD University of Maryland Elimination of clock feedthrough University of Maryland Test Structures for Low Power Analog Memory University of Maryland FOUR-PORT EAR-TYPE TRANSMISSION LATTICE FILTER University of Maryland ESD TEST STRUCTURES University of Maryland Schottky diodes for rf use University of Maryland switched current circuit University of Maryland Testbench On A Chip University of Maryland Circuits of multiplier, OP-amp, and A/D converter. University of Maryland Testbench On A Chip University of Maryland Inverters, Comparators, flip-flops, schmitt-triggered University of Maryland buffer, A/D converter. University of Maryland A chip containing ring oscillators with bonding pads between stages and without. University of Maryland Purpose: examining the effect of pad parasitics on digital circuit operation. University of Maryland A chip to examine the slowing effects of bonding pads on digital circuits, and crosstalk/interference effects. University of Maryland, Baltimore 16 bit risc microprocessor implementing 30 instructions University of Maryland, Baltimore Class project University of Michigan General Purpose Groundskeeping Device designed at Univ. of University of Michigan Michigan in Fall term, 2000 by Group2 (Densmore, Gershkovich, University of Michigan Pann and Pezda). University of Michigan As part of the PowerPC Ultra-Fast Multi-Chip Module Architecture (PUMA) project at the University of Michigan, University of Michigan a 32-bit dual-issue 4-way superscalar PowerPC fixed point unit microprocessor was designed. The processor University of Michigan implements a majority of the integer instructions of the PowerPC ISA University of Michigan High Performance MEMS-Based On-Chip Clock Generation for Embedded Microprocessors University of Michigan sigma-delta readout for capacitive sensors University of Minnesota, Duluth Campus Sound Chip having 3 channel square wave generator, University of Minnesota, Duluth Campus each channel has four outputs which can be connected University of Minnesota, Duluth Campus to an external D/A converter to vary output volume. University of Minnesota, Duluth Campus 32 bit multiplying DAC University of Minnesota, Duluth Campus 8-bit ALU University of Minnesota, Duluth Campus A high speed 8-bit ALU with two 8-bit inputs, a 16-bit output and University of Minnesota, Duluth Campus 8 functions (8x8 multiply, add, subtract, invert, left/right shift with both 0 & 1) University of Minnesota, Duluth Campus An 8-bit by 8-bit Multiplier University of Minnesota, Duluth Campus A variable length/ variable frequency tone generater with memory for up to 8 tones. It takes multiple inputs to store and play tones. University of Minnesota, Duluth Campus This is the first chip of two in our project. The first Chip samples data from an accelerometer and stores generated values to a compact flash card. The second chip reads data from the compact flash card and transmits it via serial University of Minnesota, Duluth Campus connection to a pc for analysis. University of Minnesota, Duluth Campus This chip accepts commands from a PC over a serial connection. It then processes those commands, and reads the requested data from a compact flash card, and transmits the data back to the PC over a serial connection. University of Missouri-Columbia A set of circuits to start studying adiabatic low power circuits. University of Nebraska - Lincoln This is a characterization chip for dual-gate MOS structures. There are a number University of Nebraska - Lincoln of dual-gate MOS devices with various geometries within the pad frame. University of Nebraska - Lincoln This is the first in a series of three EE 470-S01 chips designed by B. Fast, Z. Zobel, and A.J. Mogis University of Nebraska - Lincoln This is the second in a series of three 470spring01 chips designed by J. Schroeder and P. Cantu University of Nebraska - Lincoln This is the last in a series of three 470spring01 chips designed by B. Trenkle and E. Kamin University of Nebraska - Lincoln This is a multi-project chip designed by students who took the "EE 469 University of Nebraska - Lincoln Analog Integrated Circuit Design" course offered in the Fall of 2001 at University of Nebraska - Lincoln the University of Nebraska - Dept. of EE. The chips contains 6 designs, University of Nebraska - Lincoln which are: 1) VCO, 2) Comparator, 3) Comparator with track and hold, University of Nebraska - Lincoln 4) OTA, 5) Multiplier, 6) Fully compansated Opamp with built-in bias University of Nebraska - Lincoln circuit. University of Nebraska - Lincoln This is a class project chip. It incorporates 3 CLBs that acts as a scaled-down FPGA. University of Nebraska - Lincoln This is a class project chip incorporating a 7-segment display driver and University of Nebraska - Lincoln a 4-bit mirror-adder University of North Carolina, Charlotte Weldon/norbert, delta sigma ADC, MixSig Fall, 12/00 University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte The students in ECGR 5133 VLSI Systems Design (Fall 2000) University of North Carolina, Charlotte designed an 8-bit ALU-based processor with 16 instructions, University of North Carolina, Charlotte a 32-word program memory, input and output registers. University of North Carolina, Charlotte Weldon/mickharr, ami05, MixSig Fall, 12/00 University of North Carolina, Charlotte Radio Front End University of North Carolina, Charlotte Weldon/mh, ADK12, MixSig Fall, 12/00 University of North Carolina, Charlotte Weldon/mh, ADK12, MixSig Fall, 12/00 University of North Carolina, Charlotte MIXSIG project ami12 sucadc, andrtayl,jacheath University of North Carolina, Charlotte MIXSIG project ami12 iqmod, jaeastri/dtschuma University of North Carolina, Charlotte MIXSIG project ami12 iqmod, sushi/konrad University of North Carolina, Charlotte DFT Makki Scott Thomas University of North Carolina, Charlotte This is a test pattern generator for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte This is a test pattern generator for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte This is a test pattern generator for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte This is a output response analyzer for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte This is a output response analyzer for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte This is a output response analyzer for a Built-In Self-Test University of North Carolina, Charlotte of mixed-signal systems designed during the fall semester University of North Carolina, Charlotte 2001 in ECGR4433/5133 Intro to VLSI Systems Design. University of North Carolina, Charlotte project ami12 dac8bit, konrad University of North Carolina, Charlotte MIXSIG project ami12 cb radio jagardne/bclark University of North Carolina, Charlotte research project ami05 iddt2, tpw/konrad University of North Carolina, Charlotte DFT Makki Scott Thomas University of North Carolina, Charlotte SRAMCELLS MAKKI SURIYA KUMAR University of North Carolina, Charlotte SRAMRINGOSC MAKKI SURIYA KUMAR University of North Carolina, Charlotte IDDT SENSOR MAKKI ADAM EASTRIDGE University of North Carolina, Charlotte IDDT SENSOR MAKKI ADAM EASTRIDGE University of North Carolina, Charlotte IDDT SENSOR MAKKI ADAM EASTRIDGE University of North Carolina, Charlotte IDDTSRAM MAKKI SURIYA University of North Carolina, Charlotte INVERTERS MAKKI SAI University of North Carolina, Charlotte NANDNOR MAKKI SAI University of North Carolina, Charlotte AOI21 MAKKI SAI University of North Carolina, Charlotte OAI21 MAKKI SAI University of Notre Dame blue music chip University of Notre Dame dual-ported RAM cell and biasing University of Notre Dame Data acqusition chip--class project University of Notre Dame data acquisition chip--class project University of Notre Dame 1 GHz Clock Divider University of Notre Dame Data Acquisition Chip, class project University of Pennsylvania In this design project a synchrony detector is being built as one University of Pennsylvania part of a front end processor to a human auditory based speech University of Pennsylvania recognition system. The synchrony detector models the frequency University of Pennsylvania recognition system in the inner ear by outputting a voltage based on the University of Pennsylvania synchrony of the input signal to a desired frequency. This detection University of Pennsylvania scheme will be used on a range of frequencies to determine the full University of Pennsylvania spectral content of the speech signal. The circuit operates using analog University of Pennsylvania integrated circuit technology to perform signal analysis using math University of Pennsylvania operators and delay lines. The circuit has been designed and tested to University of Pennsylvania specification, i.e. the output of the synchrony detector is between 0 and University of Pennsylvania -2.5 volts, and the layout for the integrated circuit is currently University of Pennsylvania underway. University of Pennsylvania The goal of this project is to create a CMOS University of Pennsylvania digital camera that would have a logarithmic response to light intensity University of Pennsylvania allowing a much greater range of intensity to be captured. The camera University of Pennsylvania chip will consist of a 32 x 32 array of these logarithmic pixels University of Pennsylvania accompanied by the architecture required to output the the image University of Pennsylvania captured onto a standard computer display. Additionally there is a University of Pennsylvania correlated double sampling (CDS) system to reduce noise on the output as University of Pennsylvania well as several test structures. University of Pennsylvania A CMOS digital camera with Active Pixel Sensors and CDS. The pixel array University of Pennsylvania is 24 rows by 48 columns. The control logic is accomplished by series University of Pennsylvania connected S-R flip-flop shift registers connected to signal switches. University of Pennsylvania Camera will capture polarized light information and produce double University of Pennsylvania readouts for offchip summing and differencing. University of Pennsylvania This chip contains a small array of a new digital pixel camera. The camera allows differencing of neighboring pixels. In addition several test structures have been added to evaluate and test the various components of the system University of Portland Student VLSI Design Project (rpm chip) University of Portland Student VLSI Design Project (wc1 chip) University of Portland Student VLSI Design Project (wc2 chip) University of Portland Student VLSI Design Project (sim_sm chip) University of Portland Student VLSI Design Project (sim_pu chip) University of Portland Student VLSI Design Project (sb chip) University of Portland Student VLSI Design Project (hds chip) University of Portland Student VLSI Design Project (tanner chip) University of Portland Student VLSI Design Project (dac1 chip) University of Portland Student VLSI Design Project (dac2 chip) University of Rhode Island 63Modulator University of Rhode Island combination lock University of Rhode Island static memory University of Rhode Island 1-1-1-1 cascade/mash University of Rhode Island 1-1-1-1 cascade/mash University of Rhode Island Fish Tag '01 University of Rhode Island Serial Mutliplier University of Rhode Island 2k-bit Static RAM University of Rhode Island Fish Tag Subsys University of Rhode Island 6-3 Modulator Update ... University of Rhode Island Fish Tag Chip University of Rhode Island Correlation Rx with SCF University of Rhode Island State Machine + Memory FT. University of Rhode Island 6-3 Modulator University of Rhode Island ELE491 Special Problems Semester: Spring 2001 University of Rhode Island Wai Yung Project: 2048 Bit SRAM University of Rhode Island ELE 591 - Special Problems - Spring 2001 University of Rhode Island Student: Prasan Kasturi University of Rhode Island Project: 8 bit Serial-Parallel Multiplier University of Rhode Island FT SCF Prototype University of Rhode Island FT Cntrl Prototype University of Rhode Island Chip104 SCF University of Rhode Island SCF & Amplifiers University of Rhode Island SC test filters for sonar receiver project University of Rhode Island Battery check, thermal sensor and 10 bit ADC for fishtrack project University of Rhode Island Digital correlator and crystal oscillator for fishtrack project University of Tennessee ECE 651 student project by Andrew Moor and Aaron Symko. University of Tennessee ECE 651 student project by Eric Bolton and Brian Chesney University of Tennessee ECE 651 student project by Mohammad Ahad and Sowmyan Rajagopolan. University of Tennessee ECE 651 student project by Anand Ananthanarayanan and Duncan Earl. University of Tennessee This is a ECE 651 student project by Jung Suh and Ioannis Zapitis. University of Tennessee This is a ECE 651 student project by Z. Chen and Charles Landen. University of Tennessee This student ECE 651 project was designed in Fall 99 by Xiaoquan Fu and Chung Ku. University of Tennessee This student ECE 651 project was designed in Fall 99 by Nabil Kerkiz and Fuat Karakaya. University of Tennessee This student ECE 651 project was designed in Fall 99 by Marc Royer and Millat Khandaker. University of Tennessee This project contains custom designs which were drawn using Cadence Virtuoso and simulated using Cadence Verilog-XL and Cadence Spectre. University of Tennessee A LOW JITTER VCO AND FREQUENCY DIVIDER FOR FREQUENCY SYNTHESIZER APPLICATIONS University of Tennessee LC VCO Design Using on-chip Inductors University of Texas at Dallas Current mode transmitter driver with self-calibration. University of Texas at Dallas Photo sensor array for wide dynamic range 2D motion detection circuits University of Texas at Dallas The design implements a 32X8 Content University of Texas at Dallas addressablememory. In addition to storage and University of Texas at Dallas retrieval functions, the CAM can be used for pattern University of Texas at Dallas matching. The data is thus identified by content University of Texas at Dallas rather than address. Such a scheme is very useful in University of Texas at Dallas look-up table, cache memory, pattern recognition and University of Texas at Dallas many other applications. The CAM has been designed to University of Texas at Dallas perform READ, WRITE, SEARCH and DELETE operations. It University of Texas at Dallas is a synchronous design and all operations are University of Texas at Dallas performed over one cycle of an externally applied University of Texas at Dallas CLOCK signal. University of Texas at Dallas The second run for accurate current mode driver. (previous project: 63096) University of Texas at Dallas The design implements a 32X8 Content University of Texas at Dallas addressablememory. In addition to storage and University of Texas at Dallas retrieval functions, the CAM can be used for pattern University of Texas at Dallas matching. The data is thus identified by content University of Texas at Dallas rather than address. Such a scheme is very useful in University of Texas at Dallas look-up table, cache memory, pattern recognition and University of Texas at Dallas many other applications. The CAM has been designed to University of Texas at Dallas perform READ, WRITE, SEARCH and DELETE operations. University of Texas at Dallas The design implements a 32X8 Content University of Texas at Dallas addressablememory. In addition to storage and University of Texas at Dallas retrieval functions, the CAM can be used for pattern University of Texas at Dallas matching. The data is thus identified by content University of Texas at Dallas rather than address. Such a scheme is very useful in University of Texas at Dallas look-up table, cache memory, pattern recognition and University of Texas at Dallas many other applications. The CAM has been designed to University of Texas at Dallas perform READ, WRITE, SEARCH and DELETE operations. It University of Texas at Dallas is a synchronous design and all operations are University of Texas at Dallas performed over one cycle of an externally applied University of Texas at Dallas CLOCK signal. University of Texas at Dallas The design implements a 32X8 Content University of Texas at Dallas addressablememory. In addition to storage and University of Texas at Dallas retrieval functions, the CAM can be used for pattern University of Texas at Dallas matching. The data is thus identified by content University of Texas at Dallas rather than address. Such a scheme is very useful in University of Texas at Dallas look-up table, cache memory, pattern recognition and University of Texas at Dallas many other applications. The CAM has been designed to University of Texas at Dallas perform READ, WRITE, SEARCH and DELETE operations. University of Texas at Dallas Design is a 32 x 8 Content Addressable Memory. In addition to usual University of Texas at Dallas write, read and special erase functions, the CAM can be used for specific University of Texas at Dallas pattern matching. The data is thus identified by content rather than University of Texas at Dallas address. Such a scheme is very useful in look-up table, cache memory, pattern University of Texas at Dallas recognition and many other applications. The CAM has been designed to perform University of Texas at Dallas READ, WRITE, SEARCH and DELETE operations. It is a synchronous design and University of Texas at Dallas all operations are performed over one cycle of an externally applied University of Texas at Dallas CLOCK signal. University of Toledo conditional sum 8-bit adder University of Toledo transmission gate 8-bit adder University of Toledo 8-bit binary U/D counter University of Toledo jk register University of Toledo image transfer decoders University of Toledo digital phase-locked loop University of Toledo two decade up/down syncronous counter University of Toledo 8-bit D-type register University of Toledo 4-bit by 4-bit bidirectional shift register University of Toledo 8-bit unsigned integer parallel multiplier University of Toledo 8-bit unsigned integer parallel multiplier University of Toledo 8-bit positive-edge triggered D-type register University of Toledo Eight bit parallel adder University of Toledo Two-decade up/down counter University of Toledo Eight bit multiplier array University of Toledo Eight bit JK-register University of Toledo Eight bit full-adder University of Toledo 8 bit pos. edge triggered D register University of Toledo 8 bit magnitude comparator University of Toledo look-up table for f(x)=x**2 University of Utah A Capacitor type Digital to Analog Converter, University of Utah which converts 8 digital input bits into an analog University of Utah voltage at the output. University of Utah 8 bit binary weighted current digital to analog converter. University of Utah 8-bit Digital to Analog Converters(CapDac) University of Utah 8bit current steering DAC(segmented) University of Utah 8Bit R-2R DAC with Current Sources University of Utah 8 bit Switched Capacitor DAC University of Utah University of Utah University of Utah 4x*bit Current_DAC University of Utah Current and R@R DACS University of Utah Amplifiers University of Utah Amplifiers University of Utah A 2-bit tunable switched-capacitor biquad filter University of Utah A Flash type ADC (4bit) and also some test circuits. University of Utah A 4 bit FLASH ADC University of Utah An 8-bit A/D Converter University of Utah 8 BIT DUAL SLOPE ANALOG TO DIGITAL CONVERTER University of Utah Switch Capacitor Filter University of Utah 4-bit Flash ADC University of Utah 8-bit Switched Capacitance DAC (0.5u AMI process) University of Utah Flash Analog-to-Digital Converter University of Utah 8 bit Dual Slope ADC University of Utah Amplifier chip using Pseudo resistors University of Utah THE PROJECT IS A FOUR BIT FLASH ADC University of Utah Dual Slope Analog to Digital Converter for University of Utah class CS6963. University of Utah THE PROJECT IS A 4 BIT FLASH ADC University of Utah folding ADC University of Utah imager test chip 1 University of Utah Hamming decoder for parrel/serial University of Utah 20 bit sequential multiplier with stoppable clocks University of Utah linear transconductor University of Utah process and cell test University of Utah Student-designed memory chip from VLSI class at the University of Utah University of Utah Student-designed processor chip from VLSI class at the University of Utah University of Utah Student-designed processor chip from VLSI class at the University of Utah University of Utah imager test chip 2 University of Virginia KoggeStone 32-bit adder University of Virginia Han Carlson 32-bit adder University of Virginia modified Han Carlson 32-bit adder University of Virginia new microelectrode array University of Washington Analog to Digital Converter University of Washington Sigma Delta Modulator University of Washington Analog to Digital Converter University of Washington Delta Modulator University of Washington Instrumentation Amplifier University of Washington Folded Cascode Operational Amplifier University of Washington Transducer base line compensator University of Wisconsin, Madison This is an educational project in analog circuit design. The goal is to implment a low-power pressure sensor output amplifier into a MHz oscillator that transmits the pressure information both in ultrasonic and RF energy domains. The goal University of Wisconsin, Madison of the project is to make a low power electronic sensor telemtery system. University of Wisconsin, Madison This design conatins a sensor conditioning opamp, A/D converter, a shift register and, RF transmitter for a general purpose RF transmitter for sensors. University of Wisconsin, Madison This project is a reiteration of a circuit for an embedded pressure sensor amplifier and transmitter for baldder pressure measurement. We have improved the design for lower power and higher pressure sensitivity. The design also has a better University of Wisconsin, Madison packaging layout for a miniature package that can be placed inside the bladder. University of Wyoming A waveform DAC. University of Wyoming A CMOS multiplier. University of Wyoming A Pseudo NMOS multiplier. University of Wyoming A waveform DAC. University of Wyoming A simple ALU. University of Wyoming A simple ALU. University of Wyoming A simple ALU. University of Wyoming Multiple frequency divider project. University of Wyoming This project consists of 16 NPN transistor pairs of different sizes that will be used as a noise source for an analog encryption engine. The project also contains two externally compensated operational amplifiers for scaling and level University of Wyoming shifting of the noise generated by one of the NPN pairs. University of Wyoming This project consists of a single externally compensated operational amplifier. University of Wyoming This project consists of a two quadrant analog multiplier, a four quadrant analog multiplier, and five poly silicon resistors for measuring process parameters. University of Wyoming This project consists of an externally compensated operational amplifier. University of Wyoming This project consists of four externally compensated operational amplifiers. Each operational amplifier has been designed to examine size/performance trade offs. University of Wyoming This project consists of four externally compensated operational amplifiers. The operational amplifiers have been designed with independent wells (where possible) in an attempt to remove body effects from the functioning of the operational University of Wyoming amplifiers. Valparaiso University 4-Bit Sequential Multiplier Valparaiso University Instructor Design Valparaiso University 4-Bit Multiplier Valparaiso University Team B Valparaiso University 4-Bit Multiplier Valparaiso University Team C Valparaiso University 4-Bit Multiplier Valparaiso University Team D Valparaiso University 4-Bit Multiplier Valparaiso University Team E Valparaiso University 4-Bit Multiplier Valparaiso University Team F Valparaiso University The design is a sequential 4-bit multiplier based on Booth's Algorithm Valparaiso University of shifting and adding. Valparaiso University The design is a sequential 4-bit multiplier using Booth's algorithm Valparaiso University of shifting and adding. Villanova University class projects Villanova University class projects Villanova University class projects Villanova University class projects Villanova University class projects Virginia Commonwealth University alu with test pads Virginia Commonwealth University alu with test pads Virginia Polytechnic Institute This circuit is a 8x8 multiplier that can be Virginia Polytechnic Institute operated in Virginia Polytechnic Institute asynchronous or synchronous mode. In synchronous mode, the inputs are Virginia Polytechnic Institute latched in on each rising clock pulse. The circuit uses a Virginia Polytechnic Institute booth-recording scheme to generate all partial products in parallel Virginia Polytechnic Institute which are then fed into a wallace tree adder and finally to a 16-bit Virginia Polytechnic Institute adder which produces the result. Virginia Polytechnic Institute 3 second debouncer, simulations run correctly, and Virginia Polytechnic Institute the simulation Virginia Polytechnic Institute results were presented in the project report last semester. Virginia Polytechnic Institute Our chip is an 8-bit 3-second debouncer. It filters Virginia Polytechnic Institute out any pulses shorter than 3 seconds and passes only those which stay for Virginia Polytechnic Institute more than that. Virginia Polytechnic Institute Our chip is an 8-bit 3-second debouncer. It filters Virginia Polytechnic Institute out any pulses shorter than 3 seconds and passes only those which are Virginia Polytechnic Institute present longer at the inputs. Virginia Polytechnic Institute The three second debouncer is a simple sequential Virginia Polytechnic Institute circuit that used to condition the input signals presented by eight input Virginia Polytechnic Institute lines. If the input Virginia Polytechnic Institute changes an remains stable at that new value for more than 3 seconds, the Virginia Polytechnic Institute output will follow the input. Thus the system ignores any zero to one or Virginia Polytechnic Institute one to zero transitions that do not last at least three seconds. Washington State University MEP-Research Account Phase 1. Washington State University See our Mini-Proposal for details! Washington State University We want it fabricated in CM018 (Mixed/Signal). How do we specify this? Washington State University fall - ee466 student projects Washington University, St. Louis Mixed-signal test chip for MDK. Wayne State University 2nd order Universal Filter Wayne State University 2nd order Universal Filter Wayne State University 2nd order universal filter Wayne State University 2nd order Universal Filter Wayne State University 2nd order Universal Filter Wayne State University 2nd order universal filter Yale University Drew Mazurek, Samuel Luckenbill 40-Bit Self-Timed Bit-Level Pipelined Ripple Carry Adder Yale University Michelle Brady and Swan Chang, Network Packet Router CAM