IBM 10SF CMOS Process

If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."

Process Description

MOSIS is offering access to the IBM 65 nm CMOS 10SF technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is available at an additional cost.

MOSIS offers this CMOS process as 9 metal layers (M1, M2, M3, M4, B1, B2, B3, EA, EB) plus LB (transfer) to DV (glass cut). This is the IBM "4_3_0_2" stack, with four thin metals over low-K dielectric, three thick metals ("2x") over low-K dielectric, and two thick ("4x") metals over TEOS/FTEOS dielectric. Supply voltages are 1.0 V core and 1.8, 2.5 V I/O.

10SF Supported Options
Please refer to the list of 10SF Supported Options page for the options available by default on MOSIS MPW runs in this technology.

Other configurations are available for dedicated runs, or on MPW runs by prior arrangement. Please contact MOSIS support for additional details, e.g. costs.

Four Gate Oxide Thicknesses Available
Although there are four gate oxide thickness options, only three can be present in any one design, and DG and TG are mutually exclusive.

1.25 nm (thin)	FETs	LVT, RVT, HVT
	Vdd	Max 1.0 V
2.2 nm (intermediate)	FETs	EG (high-speed I/O FETs)
	Vdd	1.2 V 1.5 V
5.2 nm (thick)	FETs	DG (regular I/O FETs)
	Vdd	1.8 V 2.5 V 3.3 V1
6.8 nm (also called thick)	FETs	TG (TG FETs)
	Vdd	3.3 V1

¹ This device can only be fabricated at one of IBM's foundries. All other devices can be fabricated at any one of the Common Platform (CP) foundries. The CP is a collaboration between IBM and several other foundries to provide advanced feature size fabrication. Irrespective of which foundry is used, the designer can be assured that their parts will behave as if they were fabricated at IBM.

Design Considerations
To insure that submitted data is on a 5 nm grid, please stream-out at 1 DBU = 5 nm (Cadence 0.005, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.

IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries

IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.

The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM CMOS Design Kits

Design rules supported by this technology
Only the IBM design rules will be supported for this technology.

MOSIS Technology Codes
The technology code for the 10SF process is IBM_10SF.

Parametric Test Results and SPICE Model Parameters

Contact support@mosis.com.

Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness

IBM CMOS 65 Nanometer 10SF Process
Wafer Size (milli- meters)	Reticle Size (milli- meters, approx.)	Reticle Copies Stepped on Wafer (approx.)	Turn- around Time*	Die Thickness (+/- .5 mil)		Bumped Die Thickness ** (+/- .5 mil)		Wafer Thickness
				Mils	Micro- meters	Mils	Micro- meters	Mils	Micro- meters
300	25 x 30	60	57	10	250	10	250	30	760

  * Calendar days from release to manufacturing. Does not include dicing/packaging/backlapping (for planning purposes only).

** Die thickness only. Does not include height of the bumps.
    To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.

Related Resources

MOSIS-Supported IBM Processes

IBM Technology Codes & Layer Maps

IBM Document Access