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12SOI CMOS Process
IBM Semiconductor 45 nanometer
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Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS Secure Document Server.
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 45 nanometer CMOS 12SOI technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Support System
This SOI CMOS process offers up to 10 metal layers. MOSIS is currently evaluating customer interest before settling on a standard MPW stack. Core voltages is 1.0 V. A thick oxide 1.5/1.8 V option is available.
12SOI Supported OptionsPlease refer to the list of 12SOI Supported Options page for the options available on MOSIS MPW runs in this technology. You may not submit a design containing any options or metals stack which are not listed here without prior arrangement with MOSIS.
Other configurations are available for dedicated runs or on MPW runs at an additional cost. Contact support@mosis.com for details.
Design Considerations
To insure that submitted data is on a 1 nm grid, please stream-out at 1 DBU = 1 nm (Cadence 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM CMOS Design Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for the 12SOI process is IBM_12SOI.
Parametric Test Results and SPICE Model Parameters
Test data will be provided when available.
Reticle/Wafer Size, Steps, Die and Wafer Thickness
| IBM CMOS 45 nanometer 12SOI Process |
|||||||||
|---|---|---|---|---|---|---|---|---|---|
| Wafer Size (inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) | Turn-around Time* | Die Thickness (+/- .5 mil) |
Bumped Die Thickness * (+/- .5 mil) |
Wafer Thickness | |||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | ||||
| 300 | 25 x 30 | 100 | 64 | 100 | 250 | 10 | 250 | 30 | 760 |
* Calendar days from release to manufacturing. Does not include dicing/packaging/backlapping (for planning purposes only).
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.