Products > Fab Processes > IBM > IBM SIGe & CMOS Processes
5PAe SiGe BiCMOS Process
IBM Semiconductor 0.35 Micron
Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS Secure Document Server.
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.35 micron SiGe BiCMOS 5PAe
Through Silicon Vias (TSV) process technology for prototype and low
volume fabrication. The TSVs are vertical connections etched through
the silicon wafer and filled with metal, eliminating the need for
large wire-bond pads
C4 (IBM's flip chip bumping) is subject to availability at additional
cost. Advance notice required. Please submit your inquiry through the
MOSIS Support System.
Supported metal Stack:
M1, MT, E1, MA
This BiCMOS SiGe process has 4 metals layers (M1, MT, E1, MA), 2 poly
layers, and supports QT+HT Dual Nitride MiM capacitors. The thick top
layer of metal can be used to make inductors.
Please refer to the list of
5PAe Supported Options page for the options available by default on MOSIS MPW runs in this
technology.
Other configurations are available for dedicated runs, or on MPW runs
by prior arrangement. Please
contact MOSIS support for
additional details, e.g. costs.
To insure that submitted data is on a 20 nm grid, please stream-out at 1 DBU = 20 nm (Cadence 0.020, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.
Device Voltages
| Device | Voltage |
| Thin Oxide FET | 3.3 V |
| Thick Oxide FET | 5.0 V |
| High Performance NPN | 5.5 V |
| High Breakdown NPN | 7.5 V |
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to
customers who have signed both the MOSIS customer agreement and the
IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM SiGe Design Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
The technology code for the 5PAe process is IBM_5PAE.
Parametric Test Results and SPICE Model Parameters
See Test Results for IBM 0.35 micron runsReticle/Wafer Size, Steps, Die and Wafer Thickness
|
IBM SiGe BiCMOS
0.35 Micron 5PAe Process |
||||||||
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness *
(+/- .5 mil) |
Wafer Thickness | |||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | |||
| 8 | 18 x 20 | 60 | 4 | 100 | 4 | 100 | 4 | 100 |
* Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.