Products > Fab Processes > IBM > IBM 0.18 Micron 7HV Process
7HV CMOS Process
IBM Semiconductor 0.18 Micron
Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS Secure Document Server
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.18 micron CMOS 7HV technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Support System.Supported metal Stack:
M1, M2, M3, MT, AM
This HV CMOS process allows the integration of 1.8 V, 5 V, 20 V, and 50 V devices on a single chip.
7HV Supported Options
CMOS: ThickOx NFET and PFET with 5.0 V Operations *
MiM Capacitor: 2.05 fF/µm2
Dual MiM Capacitor: 4.10 fF/µm2
PC Polysilicon (RR) Resistor *
Precision PC Polysilicon (RP) Resistor *
BEOL Metal Level Resistor K1 *
5LM-AM M1/M2/M3/MT/AM Metal Stack
ML last Metal *
AM last Metal
DV Passivation (Wirebond)
LV Passivation (C4 Bumping) *
* Options available upon request, Custom Quotation is required.
Other configurations are available for dedicated runs or on MPW runs at an additional cost. Contact support@mosis.com. for details.
Design Considerations
To insure that submitted data is on a 10 nm grid, please stream-out at 1 DBU = 10 nm (Cadence 0.010, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM CMOS Design Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for the 7HV process is IBM_7HV.
Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com for test results and SPICE model parameters.Reticle/Wafer Size, Steps, Die and Wafer Thickness
|
IBM CMOS
0.18 Micron 7HV Process |
|||||||||
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness **
(+/- .5 mil) |
Wafer Thickness | ||||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 18 x 20 | 60 | 10 | 250 | 10 | 250 | 30 | 760 | |
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.