Products > Fab Processes > IBM > IBM 180 Nanometer 7RF Process
IBM 7RF CMOS Process
180 Nanometer (180 nm)
Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS MOSIS Secure Document Server.
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.18 micron CMOS 7RF technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Secure Document Server.
Supported metal Stack:
M1, M2, M3, M4, MT, ML
This CMOS process has 6 metal layers (M1, M2, M3, M4, MT, ML) with DV
(wirebound glass cut) and supports QT+HT Dual Nitride MiM capacitors.
Supply voltages are 1.8 V core and 3.3 V I/O. 5 V transistors
available only by special request and advance notice required: contact
MOSIS Support.
7RF Supported Options
Please refer to the List of 7RF Supported Options page for the options available on MOSIS MPW runs in this technology. You may not submit a design containing any options or metals stack which are not listed here without prior arrangement with MOSIS.
Other configurations are available for dedicated runs or on MPW runs at an additional cost. Contact MOSIS Support. for details. While the process is capable of up to 8 metal layers, we offer 6 on multi-project wafer runs.
Design Considerations
To insure that submitted data is on a 10 nm grid, please stream-out
at 1 DBU = 10 nm (Cadence 0.010, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet
the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM CMOS Design Kits
Design rules supported by this technology
Only the IBM design rules will be supported for this
technology.
MOSIS Technology Codes
The technology code for the 7RF process is IBM_7RF.
Parametric Test Results and SPICE Model Parameters
See Test Results for IBM 0.18 nanometer runsReticle/Wafer Size, Steps, Die and Wafer Thickness
|
IBM CMOS
0.18 Micron 7RF Process |
||||||||
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness *
(+/- .5 mil) |
Wafer Thickness | |||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | |||
| 8 | 18 x 20 | 60 | 10 | 250 | 10 | 250 | 30 | 760 |
* Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.