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7WL SiGe BiCMOS Process
IBM Semiconductor 0.18 Micron
Information vital to preparing and submitting a design for fabrication in this process has been posted to the MOSIS Secure Document Server
All users must read the checking procedures and density requirements described in this document.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs."
Process Description
MOSIS is offering access to the IBM 0.18 micron SiGe BiCMOS 7WL technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Support System.Supported metal Stack:
M1, M2, M3, M4, MT, E1, MA
This BiCMOS SiGe process has 7 metal layers (M1, M2, M3, M4, MT, E1, MA) and supports QT-HT Dual Nitride MiM capacitor (4.1 fF/µm²). The thick top layer of metal can be used to make inductors. Supply voltages are 1.8 V core and 3.3 V I/O. For more information, see the SiGe process comparison.
7WL Supported Options
Please refer to the list of 7WL Supported Options page for the options available by default on MOSIS MPW runs in this technology.
Other configurations are available for dedicated runs, or on MPW runs by prior arrangement. Please contact MOSIS support for additional details, e.g. costs.
The stacked MiM option in this process also allows for single MiMs to be fabricated: you do not need to contact MOSIS about this.
Design Considerations
To insure that submitted data is on a 10 nm grid, please stream-out at 1 DBU = 10 nm (Cadence 0.010, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.
The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM SiGe Design Kits page are the only kits and files available.Design rules supported by this technology
Only the IBM design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for the 7WL process is IBM_7WL.
Parametric Test Results and SPICE Model Parameters
See Test Results for IBM 0.18 micron runs
Reticle/Wafer Size, Steps, Die and Wafer Thickness
|
IBM SiGe BiCMOS
0.18 Micron 7WL Process |
||||||||
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness *
(+/- .5 mil) |
Wafer Thickness | |||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | |||
| 8 | 18 x 20 | 60 | 10 | 250 | 10 | 250 | 30 | 760 |
* Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.