Products > Fab Processes > ON Semiconductor > ON Semi I3T50 Process
I3T50 Process
ON Semiconductor (formerly AMIS) 0.35 Micron
Process Description
This CMOS process has 4 metal layers. The process offers MiM capacitor, high resistive poly, and 3.3 volt digital core and I/O's. Medium voltage NPN transistor and Zener zap diode for OTP are available.
Design Rules
This process supports only the ON Semiconductor design rules.
MOSIS Technology Codes
The technology code for this process is AMI_I3T50.
Important note about insulator layers
On this process, ON Semiconductor requires that all features on the insulator layers (CONTACT, VIA) be of the single standard size. There are no exceptions for pads, logos, or anything else. Large openings are to be replaced by an array of standard sized openings.
ON Semiconductor Design Rules, Process Specifications, and SPICE Parameters
ON Semiconductor has sub-licensed MOSIS to distribute this information to customers who do not have a MyAMIS or MyON account. To obtain any of these items you must have an account with MOSIS, submit the on-line ON Semiconductor Access Request, then sign both the Confidentiality Agreement (CDA) and Design Kit License Agreement (DKLA).