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TSMC Fabrication

Technology descriptions, MPW fabrication schedule, and vendor document access procedures for the TSMC fabrication processes available through MOSIS.

TSMC Fabrication Processes

The TSMC fabrication processes available through MOSIS range from 40 nanometer to 0.35 µm. Low power, low voltage, and high voltage options are available in most of these technologies.

TSMC Fabrication Schedule

MOSIS offers access to the TSMC multiproject wafer (MPW) runs. To be considered ontime for an MPW run, layout and paperwork are due to MOSIS by 1 PM PT (Pacific/California Time) on the date listed.

TSMC Design Kits

TSMC design kits are available upon approval for MOSIS customers.

How to Access TSMC Documents

General instructions for accessing TSMC design rules and cell libraries through MOSIS.

Related Resources

MOSIS Fabrication Processes