Products > Fab Processes > TSMC > TSMC CL013G Process
CL013G Process
Taiwan Semiconductor (TSMC) 0.13 Micron
CL013G Process (Logic) Description
This process is the TSMC nominal 0.13 Cu 1P8M FSG-IMD 1.2/2.5 V non-RDL process.
This process has 1 poly layer, 8 metals: M1 through M7 thin, and M8 thick, with MD transfer metal under CB passivation. The process is for 1.2 volt applications. A thick oxide layer can be used for 2.5 volt transistors. Designs for this process require M8 in the pad stack.
Flip chip bumping and SRAM support are available. However, for these applications, please describe your requirements and request more information from support@mosis.com, as these options could involve multiple changes to the standard metals stack.
For applications requiring MiM capacitor, high-resistance poly resistor or ultra-thick topmetal (UTM8), please see the CR013G Mixed-Mode process description page.
The standard logic process (CL013G) offering includes 1.2/2.5 V nominal (standard) NFET+PFET, 1.2/2.5 V Low-Vt NFET+PFET, 1.2 V High-Vt NFET+PFET, 1.2/2.5 V Native-Vt NFET, salicide block, varactor and BJT devices, deep N-well, and thick gate oxide (for 2.5 V devices). This logic process (CL013G) uses epitaxial or non-epitaxial wafers at MOSIS' discretion.
TSMC Design Rules, Process Specifications, and SPICE Parameters
SMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request at Customer Account Management
Review the following CMP and antenna guidelines which apply to this process.
Design rules supported by this technology Only the TSMC design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for this process is TSMC13
Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC CL013G Process | |||||||
|---|---|---|---|---|---|---|---|
| Wafer Size (inches) | Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3) (± .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21x21 | 55 | 6-7 | ~10-12 | ~250-305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact support@mosis.com if these thicknesses do not meet your requirements.