Products > Fab Processes > TSMC > TSMC CL013LP Process
CL013LP Process
Taiwan Semiconductor (TSMC) 0.13 Micron
CL013LP Process (Logic) Description
This process is the TSMC 0.13 1P8M FSG 1.5/2.5 V low power process.
This process has 1 poly layer, 8 metals. The process is for 1.5 volt applications. A thick oxide layer can be used for 2.5 volt transistors.
This process uses non-epitaxial wafers. Epitaxial wafers are available at an additional cost. Specify "epitaxial wafers" in the "Options" section of the Request for Custom Quote form for pricing. To order epitaxial wafers, submit the Request for Custom Quote and select the epitaxial fabrication option from either the New Project, Fabricate, or Update form in MOSIS Project Management.
TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request at MOSIS Customer Account Manangement.
Review the following CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
Only the TSMC design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for this process is TSMC13.
Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC CL013LP Process | |||||||
|
Wafer Size
(inches) |
Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | 10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact
support@mosis.com if these
thicknesses do not meet your requirements.