Products > Fab Processes > TSMC > TSMC 0.18 Micron Process
CL018/CR018 (CM018) Process
Taiwan Semiconductor (TSMC) 0.18 Micron
1. Process Description
This CMOS process has 6 metal layers and 1 poly layer. The process is for 1.8 volt applications. A thick oxide layer can be used for 3.3 volt transistors. Designs for this process require Metal 6 in the pad stack. Flip chip bumping is available from MOSIS. Please contact MOSIS through the online support system for more information.
CL018 Process
Silicide block, thick gate oxide (3.3 V), and NT_N options are available on multiproject runs.
This logic process uses non-epitaxial wafers. Epitaxial wafers are available at an additional cost. Specify "epitaxial wafers" in the "Options" section of the Request for Custom Quote form for pricing. To order epitaxial wafers, submit the Request for Custom Quote and select the epitaxial fabrication option from either the New Project, Fabricate, or Update form in MOSIS Project Management.
CR018 (CM018) Process
CR018 (CM018) (mixed-mode) offers the above layers of CL018, plus deep n_well, ThickTopMetal (inductor), high-resistance poly, and MiM. The Thick_Top_Metal option must be explicitly specified with each design submission that requires it. MiM (Cap_Top_Metal, also known as Metal 5 Prime, to Metal 5) provides a capacitance of 1.0 fF/µm². Contact MOSIS using the online support system for 2.0 fF/µm² availability. This mixed signal/RF process uses non-epitaxial wafers.
The CR018 (CM018) process offers two threshold voltages: nominal and medium. Nominal is the default. Medium is an extra cost option. You have a choice of N (VTM_N), P (VTM_P), or both.
2. Design Rules
These processes support the following design rules
| Design Rules |
Lambda
(micrometer) |
Feature Size
(micrometer) |
Available From |
|---|---|---|---|
| SCN6M_SUBM | 0.10 | 0.18 | MOSIS in PDF |
| SCN6M_DEEP | 0.09 | 0.18 | MOSIS in PDF |
| TSMC rules | None | 0.18 | MOSIS (See Section 3) |
Note: Stacked contacts/vias are supported by this process.
Review the following CMP and antenna guidelines which apply to this process.
MOSIS Technology Codes
3. TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request at MOSIS Account Mananegement System.
4. Parametric Test Results and SPICE Model Parameters
See Test Results for TSMC_018 runs.
5. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC 0.18 Process | |||||||
|---|---|---|---|---|---|---|---|
|
Wafer Size
(inches) |
Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(±.5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21x21 | 55 | 6-7 | ~10-12 | ~250-305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact MOSIS through the online support system if these thicknesses do not meet your requirements.