Products > Fab Processes > TSMC > TSMC CL018HV Process
CL018HV Process
Taiwan Semiconductor (TSMC) 0.18 Micron
CL018HV Process Description
This process is the TSMC 0.18 1P6M 1.8/5/32 V high voltage process.This process has 1 poly layer, 6 metals.
TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request FormsReview the following CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
TSMC design rules will be supported for this technology.
MOSIS Technology CodesSee Technology Codes for TSMC CL018HV Process.
Parametric Test Results and SPICE Model Parameters
Contact MOSIS Support.Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC CL018HV Process | |||||||
|
Wafer Size
(inches) |
Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | ~10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact
MOSIS Support if these
thicknesses do not meet your requirements.