Products > Fab Processes > TSMC > TSMC CL018LP nm Process
CL018LP Process
Taiwan Semiconductor (TSMC) 0.18 Micron
1. CL018LP Process (Logic) Description
This process is the TSMC 0.18 1P6M 1.8/3.3 V low power process.
This process has 1 poly layer, 6 metals, and is for 1.8 volt applications. This process has higher device thresholds than the standard CL018G process (MOSIS TSMC18). A thick oxide layer can be used for 3.3 volt transistors.
2. TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request form by login to MOSIS Account Management.
Review the following CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
Only the TSMC design rules will be supported for this technology.
The Technology Code for this process is TSMC18LP.
3. Parametric Test Results and SPICE Model Parameters
Contact support@mosis.com.
4. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness| TSMC CL018LP Process | |||||||
|
Wafer Size
(inches) |
Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | ~10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact support@mosis.com if these thicknesses do not meet your requirements.