Products > Fab Processes > TSMC > TSMC 0.25 Micron Process
CL025/CR025 (CM025) Process
Taiwan Semiconductor (TSMC) 0.25 Micron
1. Process Description
This CMOS process has 5 metal layers and 1 poly layer. The process is for 2.5 volt applications. A thick oxide layer can be used for 3.3 volt transistors. Designs for this process require Metal 5 in the pad stack. Flip chip bumping is available from MOSIS. Please send e-mail to support@mosis.com for more information.
CL025 Process
Silicide block (RPO), thick gate oxide (3.3 V), ESD 3.3 V, and NT_N options are available on multiproject runs.
This logic process uses non-epitaxial wafers. Epitaxial wafers are available at an additional cost. Specify "epitaxial wafers" in the "Options" section of the Request for Custom Quote form for pricing. To order epitaxial wafers, submit the Request for Custom Quote and select the epitaxial fabrication option from either the New Project, Fabrication or Update form at MOSIS Project Management.
CR025 (CM025) Process
CR025 (CM025) (mixed-mode) offers the above layers of CL025 plus deep n-well, ThickTopMetal (inductor), and MiM options. The Thick_Top_Metal option must be explicitly specified with each design submission that requires it. MiM (Cap_Top_Metal, also known as Metal 4 Prime, to Metal 4) provides a capacitance of 1 fF/µm². This mixed signal/RF process (CR025 (CM025) uses non-epitaxial wafers.
The CR025 (CM025) process offers three threshold voltages: nominal, medium and Zero. Zero threshold voltage is also called depletion threshold voltage. Nominal is the default. Medium and Zero are extra cost options. For Medium you have a choice of N (VTM_N) or P (VTM_P) or both. For Zero you have a choice of N (VTD_N) or P (VTD_P) or both AND you must order Medium of the same type.
2. Design Rules
These processes support the following design rules
| Design Rules |
Lambda
(micro- meter) |
Feature Size (micro- meter) |
Available From |
| SCN5M_SUBM | 0.15 |
0.24
(after sizing) |
MOSIS in PDF |
| SCN5M_DEEP | 0.12 | 0.24 | MOSIS in PDF |
| TSMC rules | None | 0.24 | MOSIS (See Section 3) |
Note: Stacked contacts/vias are supported by this process.
Review the following CMP and antenna guidelines which apply to both sets of design rules.
MOSIS Technology Codes
See Technology Codes for TSMC 0.25 Micron Process.
Important note about insulator layers
On this process, TSMC requires that all features on the insulator layers (CONTACT, VIA, VIA2, VIA3, VIA4) be of the single standard size. There are no exceptions for pads, logos, or anything else. Large openings are to be replaced by an array of standard sized openings.
3. TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request form by login to MOSIS Account Management.
4. Parametric Test Results and SPICE Model Parameters
See
Test Results for TSMC_025SPPM runs.5. Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC 0.25 Process | |||||||
|
Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | ~10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact support@mosis.com if these thicknesses do not meet your requirements.