Products > Fab Processes > TSMC > TSMC 0.35 Micron Process
CL035 (TSMC35_SIL) / CM035 (TSMC35_P2) Process
Taiwan Semiconductor (TSMC) 0.35 Micron
Process Description
These processes use non-epitaxial wafers. Epitaxial wafers are available at an additional cost. Specify "epitaxial wafers" in the "Options" section of the Custom quote form for pricing. To order epitaxial wafers, submit the Request for Custom Quote and select the epitaxial fabrication option from either the New Project, Fabricate, or Update at MOSIS Project Management.
Both TSMC35_P2 and TSMC35_SIL require Metal 4 in the pad stack. Flip chip bumping is available from MOSIS. Please send e-mail to MOSIS support for more information.
TSMC35_P2 (CM035)
TSMC35_P2 is the TSMC design technology for the double poly process (no silicide block). It supports via3 and metal4, and is for 3.3 volt applications. A thick oxide layer can be used for 5.0 volt transistors. 5 V ESD is available as an option. PiP (poly2 over poly) capacitors (850 aF/µm²) are available. Silicide block is not applicable to this polycided process.
TSMC35_SIL (CL035)
TSMC35_SIL is the TSMC design technology for the single poly, silicided (with silicide block for diffusion only) process. It supports 4 metal layers, and is for 3.3 volt applications. A thick oxide layer can be used for 5.0 volt transistors. 5 V ESD is available as an option.
Design Rules
These processes support the following design rules
| Design Rules |
Lambda
(micro- meter) |
Feature Size
(micro- meter) |
Available From |
|---|---|---|---|
| SCMOS_SUBM | 0.20 |
0.35
(after sizing) |
MOSIS in PDF |
| SCMOS | 0.25 |
0.35
(after sizing) |
MOSIS in PDF |
| TSMC rules | None | 0.35 | MOSIS (See Section 3) |
Note: Stacked contacts/vias are supported by this process.
Review the following CMP and antenna guidelines which apply to this process.
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MOSIS Technology Codes
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See Technology Codes and Layer Maps for TSMC 0.35 Micron
4 Metal, 2 Poly, Polycide Process
4 Metal, 1 Poly, Silicide Process
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Important note about insulator layers
- On this process, TSMC requires that all features on the insulator layers (CONTACT, VIA, VIA2, VIA3) be of the single standard size. There are no exceptions for pads, logos, or anything else. Large openings are to be replaced by an array of standard sized openings.
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TSMC Design Rules, Process Specifications, and SPICE Parameters
- TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request at MOSIS Customer Account Management.
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Parametric Test Results and SPICE Model Parameters
- See
Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC 0.35 Process | |||||||
|---|---|---|---|---|---|---|---|
| Reticle Size (milli- meters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | |||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | ~10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact
support@mosis.com if these
thicknesses do not meet your requirements.