Products > Fab Processes > TSMC > TSMC CL035HV Process
CL035HV Process
Taiwan Semiconductor (TSMC) 0.35 Micron
CL035HV Process Description
This process is the TSMC 0.35 2P4M 3.3/15 V high voltage process, has 2 poly layers and 4 metals. The 0.35 µm HV DDD processes uses anneal wafers (argon annealed wafers); the BCD process uses Hi-Wafer (hydrogen annealed wafer).TSMC Design Rules, Process Specifications, and SPICE Parameters
TSMC has sub-licensed MOSIS to distribute this information to approved customers who have an account with MOSIS and submit the online TSMC Access Request by logging into MOSIS Account Management.
Review the following CMP and antenna guidelines which apply to this process.
Design rules supported by this technology
Only the TSMC design rules will be supported for this technology.
MOSIS Technology Codes
See Technology Codes for TSMC CL035HV Process.
Parametric Test Results and SPICE Model Parameters
Contact MOSIS Support.Reticle/Wafer Size, Steps, Turnaround Time, Die and Wafer Thickness
| TSMC CL035HV Process | |||||||
|
Wafer Size
(inches) |
Reticle Size (millimeters, approx.) (1) | Reticle Copies Stepped on Wafer (approx.) | Turn- around Time (weeks, approx.) (2) |
Die Thickness (3)
(+/- .5 mil) |
Wafer Thickness (3) | ||
| Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 21 x 21 | 55 | 6 - 7 | ~10 - 12 | ~250 - 305 | 30 | 760 |
(1) Smaller sizes are available.
(2) Packaging not included in turnaround time.
(3) Contact
MOSIS support if these
thicknesses do not meet your requirements.