Digital Design Flow
Synthesis to place and route (with verification) design flows are available as listed below.
Aragio offers I/Os (pads), and memory generators to commercial firms for the GF 65nm (10SF, 10LPe) processes.
ARM offers digital standard cell libraries, I/Os (pads) and memory generators to commercial firms for a variety of processes.
For academics and research organizations, please contact the ARM University Program.
For both commercial and non-commercial users, access to ARM IP is available via ARM Design Start.