SCMOS Design Kits

SCMOS Design Flow

Projects submitted to MOSIS for fabrication can be designed using either layout design rules and layers specific to a process (vendor native rules) or (for some processes) vendor-independent, scalable rules (SCMOS rules). These rule sets cannot be mixed within a design.

The table below contains links to design kits, technology files, cell libraries, IP, and other design support for a variety of CAD tools for various processes available through MOSIS that use SCMOS rules.

Foundry Comparable Process1 Technology Codes
(Link to Layer Map)
Lambda Design Kit DRC, LVS, Extraction Cell Libraries Pads
ON Semi 0.50 micron, 1P3M, C5 SCN3M SCN3M_SUBM 0.35 0.30 Mentor ASIC Design Kit,

Magic ,

Electric
Cadence, Diva

Polyteda
Tanner (SUBM)
  CIF
  GDS

Oklahoma State (SUBM3)
SCMOS_SUBM
  CIF
  GDS

Magic

0.50 micron, 2P3M, C5 SCN3ME SCN3ME_SUBM 0.35 0.30 Mentor ASIC Design Kit,

Magic,

Electric
Polyteda Tanner (SUBM)
  CIF
  GDS

Oklahoma State (SUBM3)
SCN3ME_SUBM

Magic


1 MOSIS has not issued SCMOS design rules for some vendor-supported options. Most non-standard options (for example, medium threshold voltage) are available only for projects designed using the vendor set of layers and rules.
2 The Diva DRC deck contains all rules from the MOSIS SCMOS User's Manual 8.0 except for some DEEP rules and wide-metal rules.

Related Resources

Tale of an IC Design Engineer (SJSU)

Cadence Tutorial (Worcester Polytechnic Institute)